CS44800-CQZ Cirrus Logic Inc, CS44800-CQZ Datasheet - Page 74

• Manufacturer Part Number: CS44800-CQZ
• Description: IC,Audio Power Amplifier Controller,CMOS,QFP,64PIN
• Manufacturer: Cirrus Logic Inc
• Type: Digital Amplifier Controllerr

Specifications of CS44800-CQZ

• Applications: Automotive Systems
• Mounting Type: Surface Mount
• Package / Case: 64-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 598-1532 - BOARD EVAL FOR CS44800 PWM CTRL
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 598-1070

74
7.32.2 Power Supply Rejection Reset (PSR_RESET)
7.32.3 Power Supply Rejection Feedback Enable (FEEDBACK_EN)
7.32.4 Power Supply Sync Clock Divider Settings (PS_SYNC_DIV[2:0])
7.33
7.33.1 Decimator Shift (DEC_SHIFT[2:0])
DEC_SCALE15 DEC_SCALE14 DEC_SCALE13 DEC_SCALE12 DEC_SCALE11 DEC_SCALE10 DEC_SCALE09 DEC_SCALE08
DEC_SCALE07 DEC_SCALE06 DEC_SCALE05 DEC_SCALE04 DEC_SCALE03 DEC_SCALE02 DEC_SCALE01 DEC_SCALE00
RESERVED
7
7
7
Decimator Shift/Scale (addresses 35h, 36h, 37h)
Default = 0
0 - force reset condition
1 - remove reset condition
Function:
This bit is used to assert a reset condition to the on-card PSR components. When set to a ‘0’b, the
PSR_RESET signal will be asserted low. The reset condition will continue as long as this bit is set to a
‘0’b. This bit must be set to a ‘1’b for proper PSR operation.
Default = 0
0 - disable
1 - enable
Function:
Enables the internal power supply rejection feedback logic.
Default = 000
Function:
These three bits determine the divider for the XTAL clock signal for generating the PS_SYNC clock signal.
Default = 010
Function:
These bits are used to scale the power supply reading
ing the PSR feedback calibration sequence. The combination of shift and scale factors
(DEC_SCALE[18:0]*2^(DEC_SHIFT[2:0])) can be viewed as a floating point coefficient. The floating point
coefficient will be determined during the PSR feedback calibration sequence. See
(DEC_SCALE[18:0])
DEC_SHIFT2
6
6
6
DEC_SHIFT1
register description and
Table 17. Power Supply Sync Clock Divider Settings
PS_SYNC_DIV[2:0]
5
5
5
000
001
010
011
100
101
110
DEC_SHIFT0
4
4
4
“Recommended PSR Calibration Sequence” on page
PS_SYNC Clock Divider
RESERVED
Output Disabled
Divide by 1024
Divide by 128
Divide by 256
Divide by 512
Divide by 32
Divide by 64
3
3
3
(Decimator Outd (addresses 3Bh, 3Ch,
DEC_SCALE18 DEC_SCALE17 DEC_SCALE16
2
2
2
1
1
1
Decimator Scale
CS44800
3Dh)) dur-
DS632F1
0
0
0
44.