DSPIC30F1010-20E/SO Microchip Technology, DSPIC30F1010-20E/SO Datasheet - Page 207
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DSPIC30F1010-20E/SO
Manufacturer Part Number
DSPIC30F1010-20E/SO
Description
6KB, Flash, 256bytes-RAM, 30MIPS, 21I/O, 16-bit Family,nanoWatt 28 SOIC .300in T
Manufacturer
Microchip Technology
Series
dsPIC™ 30Fr
Datasheets
1.AC164335.pdf
(286 pages)
2.DM300023.pdf
(22 pages)
3.DM300023.pdf
(18 pages)
4.DSPIC30F2011-20ISO.pdf
(66 pages)
5.DSPIC30F2011-20IP.pdf
(26 pages)
6.DSPIC30F1010-30ISO.pdf
(26 pages)
7.DSPIC30F1010-30ISO.pdf
(50 pages)
Specifications of DSPIC30F1010-20E/SO
Core Processor
dsPIC
Core Size
16-Bit
Speed
20 MIPS
Connectivity
I²C, IrDA, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
21
Program Memory Size
6KB (2K x 24)
Program Memory Type
FLASH
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 6x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
28-SOIC (7.5mm Width)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
DM300023 - KIT DEMO DSPICDEM SMPS BUCKDV164005 - KIT ICD2 SIMPLE SUIT W/USB CABLE
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Available stocks
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Quantity
Price
Company:
Part Number:
DSPIC30F1010-20E/SO
Manufacturer:
Microchip Technology
Quantity:
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Manufacturer:
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- AC164335 PDF datasheet
- DM300023 PDF datasheet #2
- DM300023 PDF datasheet #3
- DSPIC30F2011-20ISO PDF datasheet #4
- DSPIC30F2011-20IP PDF datasheet #5
- DSPIC30F1010-30ISO PDF datasheet #6
- DSPIC30F1010-30ISO PDF datasheet #7
- Current page: 207 of 286
- Download datasheet (5Mb)
18.2.1
Because the OSCCON register allows clock switching
and clock scaling, a write to OSCCON is intentionally
made difficult. To write to the OSCCON low byte, this
exact sequence must be executed without any other
instructions in between:
• Byte Write “46h” to OSCCON low
• Byte Write “57h” to OSCCON low
• Byte Write is allowed for one instruction cycle
To write to the OSCCON high byte, this exact
sequence must be executed without any other instruc-
tions in between:
• Byte Write “78h” to OSCCON high
• Byte Write “9Ah” to OSCCON high
• Byte Write is allowed for one instruction cycle
18.3
Figure 18-2 shows the derivation of the system clock
F
quency of 480MHz (high-range FRC option for
industrial temperature parts with PLL and TUN<3:0> =
0111 bit settings). This signal is used by the Power
Supply PWM module, and is 32 times the input PLL fre-
quency.
FIGURE 18-2:
© 2006 Microchip Technology Inc.
CY
mov.b W0,OSCCON
mov.b W0,OSCCON + 1
. The PLL in Figure 18-1 outputs a maximum fre-
PLL – 192-480 MH
Primary Oscillator
Oscillator Configurations
F
ACCIDENTAL WRITE PROTECTION
PLL
FRC
Z
Oscillator Configuration Bits
SYSTEM CLOCK AND FADC DERIVATION
Divide
Divide
By 2
By 8
F
OSC
96-240 MH
24-60 MH
Preliminary
Z
Z
Assuming the high-range FRC option is selected on an
industrial temperature rated part, the 480 MHz PLL
clock signal is divided by 2, providing a 240 MHz signal,
which drives the ADC Module. The same 480 MHz sig-
nal is also divided by 8 to produce the 60 MHz signal,
which is one of the inputs to the F
other input to this multiplexer is the FOSC input clock
source (either the Primary Oscillator or the FRC)
divided by 2. When the PLL is enabled, F
When the PLL is disabled, F
This method derives the 480 MHz clock:
• FRC Clock with high-range Option and TUN<3:0>
• PLL enabled
• PWM clock = 15 x 32 = 480 MHz
• F
If the PLL is disabled,
• FRC Clock (with high-range Option and
• F
= 0111 is = 15 MHz
TUN<3:0> = 0111) is = 15MHz
dsPIC30F1010/202X
PLL Enable
CY
CY
= 480 MHz/16 = 30 MHz = 30 MIPS
= 15 MHz/2 = 7.5 MHz = 7.5 MIPS
1
0
PLL Enable
1
0
Divide
By 2
CY
= F
OSC
CY
DS70178C-page 205
F
ADC
multiplexer. The
/2.
CY
= F
F
CY
PLL
/16.
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