DSPIC30F1010-20E/SO Microchip Technology, DSPIC30F1010-20E/SO Datasheet - Page 50
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DSPIC30F1010-20E/SO
Manufacturer Part Number
DSPIC30F1010-20E/SO
Description
6KB, Flash, 256bytes-RAM, 30MIPS, 21I/O, 16-bit Family,nanoWatt 28 SOIC .300in T
Manufacturer
Microchip Technology
Series
dsPIC™ 30Fr
Datasheets
1.AC164335.pdf
(286 pages)
2.DM300023.pdf
(22 pages)
3.DM300023.pdf
(18 pages)
4.DSPIC30F2011-20ISO.pdf
(66 pages)
5.DSPIC30F2011-20IP.pdf
(26 pages)
6.DSPIC30F1010-30ISO.pdf
(26 pages)
7.DSPIC30F1010-30ISO.pdf
(50 pages)
Specifications of DSPIC30F1010-20E/SO
Core Processor
dsPIC
Core Size
16-Bit
Speed
20 MIPS
Connectivity
I²C, IrDA, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
21
Program Memory Size
6KB (2K x 24)
Program Memory Type
FLASH
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 6x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
28-SOIC (7.5mm Width)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
DM300023 - KIT DEMO DSPICDEM SMPS BUCKDV164005 - KIT ICD2 SIMPLE SUIT W/USB CABLE
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Available stocks
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Part Number:
DSPIC30F1010-20E/SO
Manufacturer:
Microchip Technology
Quantity:
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Manufacturer:
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- AC164335 PDF datasheet
- DM300023 PDF datasheet #2
- DM300023 PDF datasheet #3
- DSPIC30F2011-20ISO PDF datasheet #4
- DSPIC30F2011-20IP PDF datasheet #5
- DSPIC30F1010-30ISO PDF datasheet #6
- DSPIC30F1010-30ISO PDF datasheet #7
- Current page: 50 of 286
- Download datasheet (5Mb)
dsPIC30F1010/202X
5.1
The user-assignable Interrupt Priority (IP<2:0>) bits for
each individual interrupt source are located in the Least
Significant 3 bits of each nibble, within the IPCx
register(s). Bit 3 of each nibble is not used and is read
as a ‘0’. These bits define the priority level assigned to
a particular interrupt by the user.
Since more than one interrupt request source may be
assigned to a specific user specified priority level, a
means is provided to assign priority within a given level.
This method is called “Natural Order Priority” and is
final.
Natural order priority is determined by the position of an
interrupt in the vector table, and only affects interrupt
operation when multiple interrupts with the same user-
assigned priority become pending at the same time.
Table 5-1 lists the interrupt numbers and interrupt
sources for the dsPIC DSC devices and their
associated vector numbers.
The ability for the user to assign every interrupt to one
of seven priority levels implies that the user can assign
a very high overall priority level to an interrupt with a
low natural order priority. The INT0 (external interrupt
0) may be assigned to priority level 1, thus giving it a
very low effective priority.
DS70178C-page 48
Note:
Note 1: The natural order priority scheme has 0
2: The natural order priority number is the
Interrupt Priority
The user selectable priority levels start at
0, as the lowest priority, and level 7, as the
highest priority.
as the highest priority and 53 as the
lowest priority.
same as the INT number.
Preliminary
TABLE 5-1:
Highest Natural Order Priority
Lowest Natural Order Priority
Number
45-53
INT
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
0
1
2
3
4
5
6
7
8
9
Number
Vector
53-61
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
8
9
dsPIC30F1010/202X
INTERRUPT VECTOR TABLE
INT0 – External Interrupt 0
IC1 – Input Capture 1
OC1 – Output Compare 1
T1 – Timer 1
Reserved
OC2 – Output Compare 2
T2 – Timer 2
T3 – Timer 3
SPI1
U1RX – UART1 Receiver
U1TX – UART1 Transmitter
ADC – ADC Convert Done
NVM – NVM Write Complete
SI2C – I
MI2C – I
Reserved
INT1 – External Interrupt 1
INT2 – External Interrupt 2
PWM Gen#1
PWM Gen#2
PWM Gen#3
PWM Gen#4
Reserved
Reserved
Reserved
Reserved
CN – Input Change Notification
Reserved
Analog Comparator 1
Analog Comparator 2
Analog Comparator 3
Analog Comparator 4
Reserved
Reserved
Reserved
Reserved
ADC Pair 0 Conversion Done
ADC Pair 1 Conversion Done
ADC Pair 2 Conversion Done
ADC Pair 3 Conversion Done
ADC Pair 4 Conversion Done
ADC Pair 5 Conversion Done
Reserved
Reserved
Reserved
PWM Special Event Trigger
© 2006 Microchip Technology Inc.
2
Interrupt Source
2
C™ Slave Event
C Master Event
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