EP9307-CR Cirrus Logic Inc, EP9307-CR Datasheet - Page 123

• Manufacturer Part Number: EP9307-CR
• Description: IC,MICROPROCESSOR,32-BIT,CMOS,BGA,272PIN,PLASTIC
• Manufacturer: Cirrus Logic Inc
• Series: EP9r

Specifications of EP9307-CR

• Rohs Compliant: NO
• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, Ethernet, I²C, IrDA, Keypad/Touchscreen, SPI, UART/USART, USB
• Peripherals: AC'97, DMA, I&sup2:S, LCD, LED, MaverickKey, POR, PWM, WDT
• Number Of I /o: 14
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Data Converters: A/D 8x12b
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 272-TFBGA
• Processor Series: EP93xx
• Core: ARM920T
• Data Bus Width: 32 bit
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: EDB9307A-Z
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With: 598-1133 - KIT DEVELOPMENT EP9307 ARM9
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: No
• Other names: 598-1254

DS785UM1
Note: ASYNC boot mode is the preferred boot mode type for new designs.
EECLK EEDAT BOOT1
0
0
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
BOOT0 ASDO CSn[7:6]
Copyright 2007 Cirrus Logic
0
0
1
0
0
0
Table 4-1. Boot Configuration Options
1
0
1
0
x
x
0 0
0 1
1 0
1 1
0 0
0 1
1 0
1 1
0 0
0 1
1 0
1 1
0 0
0 1
1 0
1 1
xx
xx
External boot using Sync boot mode and SDCSn3.
The media type must be either SyncROM or
SyncFLASH. The selection of the bus width is
determined by latched CSn[7:6] value:
16-bit
16-bit
32-bit
32-bit
External boot using Async boot mode and CSn0. The
selection of the bus width is determined by latched
CSn[7:6] value:
8-bit
16-bit
32-bit
32-bit
Internal boot from UART1.
Internal SPI boot if HeaderID is found.
Internal boot using SYNC boot mode at the chip select
where the HeaderID exists. The selection of the bus
width is determined by latched CSn[7:6] value:
16-bit
16-bit
32-bit
32-bit
See memory map in
boot mode.
Internal boot using ASYNC boot mode at the chip
select where the HeaderID exists. The selection of the
bus width is determined by latched CSn[7:6] value:
8-bit
16-bit
32-bit
32-bit
See memory map in
ASYNC boot mode.
Boot Configuration
Table 2-7 on page 2-16
Table 2-7 on page 2-16
EP93xx User’s Guide
Boot ROM
for SYNC
for
4-5
4