EP9307-CR Cirrus Logic Inc, EP9307-CR Datasheet - Page 629

• Manufacturer Part Number: EP9307-CR
• Description: IC,MICROPROCESSOR,32-BIT,CMOS,BGA,272PIN,PLASTIC
• Manufacturer: Cirrus Logic Inc
• Series: EP9r

Specifications of EP9307-CR

• Rohs Compliant: NO
• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, Ethernet, I²C, IrDA, Keypad/Touchscreen, SPI, UART/USART, USB
• Peripherals: AC'97, DMA, I&sup2:S, LCD, LED, MaverickKey, POR, PWM, WDT
• Number Of I /o: 14
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Data Converters: A/D 8x12b
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 272-TFBGA
• Processor Series: EP93xx
• Core: ARM920T
• Data Bus Width: 32 bit
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: EDB9307A-Z
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With: 598-1133 - KIT DEVELOPMENT EP9307 ARM9
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: No
• Other names: 598-1254

MIMR
DS785UM1
31
15
Address:
Default:
Definition:
Bit Descriptions:
30
14
29
13
28
12
RFS:
TAB:
TFC:
TFS:
0x808B_0084 - Read/Write
0x0000_0000
MIR Interrupt Mask Register.
RSVD:
RFL:
RIL:
RSVD
27
11
26
10
Copyright 2007 Cirrus Logic
25
9
Receive buffer Service Request (read only).
0 - Receive buffer is empty or the receiver is discarding
data or the receiver is disabled.
1 - Receive buffer is not empty and the receiver is
enabled, DMA service request signaled.
Transmit Frame Aborted. Set to “1” when a transmitted
frame is terminated with an abort. This will only occur if the
TUS bit is set in the IrCtrl register. Writing a “1” to this bit
clears it.
Transmitted Frame Complete. Set to “1” whenever a
transmitted frame completes, whether it is terminated with
a CRC followed by a stop flag or terminated with an abort.
Writing a “1” to this bit clears it.
Transmit buffer Service Request (read only).
0 - Transmit buffer is full or transmitter disabled.
1 - Transmit buffer is not full and the transmitter is
enabled, DMA service is signaled.
The bit is automatically cleared after the buffer is filled.
Reserved. Unknown During Read.
RFL mask bit. When high, the MIR RFL status can
generate an interrupt.
RIL mask bit. When high, the MIR RIL status can generate
an interrupt.
24
8
RSVD
23
7
RFL
22
6
RIL
21
5
RFC
20
4
RFS
19
3
EP93xx User’s Guide
TAB
18
2
TFC
17
1
17-33
TFS
IrDA
16
0
17