EP9307-CR Cirrus Logic Inc, EP9307-CR Datasheet - Page 578

• Manufacturer Part Number: EP9307-CR
• Description: IC,MICROPROCESSOR,32-BIT,CMOS,BGA,272PIN,PLASTIC
• Manufacturer: Cirrus Logic Inc
• Series: EP9r

Specifications of EP9307-CR

• Rohs Compliant: NO
• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, Ethernet, I²C, IrDA, Keypad/Touchscreen, SPI, UART/USART, USB
• Peripherals: AC'97, DMA, I&sup2:S, LCD, LED, MaverickKey, POR, PWM, WDT
• Number Of I /o: 14
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Data Converters: A/D 8x12b
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 272-TFBGA
• Processor Series: EP93xx
• Core: ARM920T
• Data Bus Width: 32 bit
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: EDB9307A-Z
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With: 598-1133 - KIT DEVELOPMENT EP9307 ARM9
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: No
• Other names: 598-1254

16
16-2
UART3 With HDLC Encoder
EP93xx User’s Guide
16.2.2 Clocking Requirements
16.2.3 Bus Bandwidth Requirements
There are two clocks, PCLK and UARTCLK.
UARTCLK frequency must accommodate the desired range of baud rates:
The frequency of UARTCLK must also be within the required error limits for all baud rates to
be used.
To allow sufficient time to write the received data to the receive FIFO, UARTCLK must be less
than or equal to four times the frequency of PCLK:
There are two basic ways of moving data to and from the UART FIFOs:
Bandwidth requirements also depend on the selected baud rate, character size, parity
selection, number of stop bits, and spacing between characters (if receiving).
For example, assume 115,200 baud, 8-bit characters, even parity, one stop bit, no space
between characters. There are 11 bits per character, so 115,200 / 11 = 10,473 characters per
second. If both transmitting and receiving, 20,945 characters per second pass through the
UART. Accessing the UART through the DMA interface requires one access per 32-bits,
implying only 20,945 / 4 = 5,236 AHB accesses per second. Accessing the UART through the
APB requires two accesses per byte, implying 20,945 APB buss accesses.
• Direct DMA interface - this permits byte-wide access to the UART without using the
• Accessing the UART via the APB - this requires APB/AHB bus bandwidth. Then, both a
APB. The DMA block will pack or unpack individual bytes so that it reads or writes full
32-bit words rather than individual bytes.
read and write are required for each 8-bit data byte.
bit 26
TonG
x
x
x
1
F
F
F
UARTCLK
UARTCLK
UARTCLK
HC3IN
bit 15
0
1
0
x
(min) >= 32 x baud_rate(max)
(max) <= 32 x 65536 x baud_rate(min)
HC3EN
<= 4 x Fpclk
bit 14
Copyright 2007 Cirrus Logic
Table 16-2. DeviceCfg Register Bit Functions
0
1
1
0
HC1EN
bit 12
x
0
0
0
External HDLC clock input is driven by EGPIO[3].
Internal HDLC clock output drives EGPIO[3].
External HDLC clock input is driven low.
TENn output drives EGPIO[3].
Function
DS785UM1