PIC18C601-I/PT Microchip Technology, PIC18C601-I/PT Datasheet - Page 158
![IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,TQFP,64PIN,PLASTIC](/photos/6/81/68123/c04-066_pf_sml.jpg)
PIC18C601-I/PT
Manufacturer Part Number
PIC18C601-I/PT
Description
IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,TQFP,64PIN,PLASTIC
Manufacturer
Microchip Technology
Series
PIC® 18Cr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC18C601-IL.pdf
(320 pages)
3.PIC18C601-IL.pdf
(10 pages)
4.PIC18C601-IL.pdf
(10 pages)
Specifications of PIC18C601-I/PT
Rohs Compliant
YES
Core Processor
PIC
Core Size
8-Bit
Speed
25MHz
Connectivity
EBI/EMI, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Number Of I /o
26
Program Memory Type
ROMless
Ram Size
1.5K x 8
Voltage - Supply (vcc/vdd)
4.2 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
64-TFQFP
Processor Series
PIC18C
Core
PIC
Data Bus Width
8 bit
Program Memory Size
256 KB
Data Ram Size
1.5 KB
Interface Type
3-Wire, I2C, SPI, USART
Maximum Clock Frequency
25 MHz
Number Of Programmable I/os
26
Number Of Timers
4
Operating Supply Voltage
2 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
DV164005, ICE4000, DV164136
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
Details
Other names
PIC18C601I/PT
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC18C601-I/PT
Manufacturer:
MICROCHIP
Quantity:
12 000
Company:
Part Number:
PIC18C601-I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
- PIC16F616T-ISL PDF datasheet
- PIC18C601-IL PDF datasheet #2
- PIC18C601-IL PDF datasheet #3
- PIC18C601-IL PDF datasheet #4
- Current page: 158 of 320
- Download datasheet (6Mb)
PIC18C601/801
15.3.6
In Master mode, all module clocks are halted, and the
transmission/reception will remain in that state until the
device wakes from SLEEP. After the device returns to
normal mode, the module will continue to transmit/
receive data.
In Slave mode, the SPI transmit/receive shift register
operates asynchronously to the device. This allows the
device to be placed in SLEEP mode, and data to be
shifted into the SPI transmit/receive shift register.
When all eight bits have been received, the MSSP
interrupt flag bit will be set and, if enabled, will wake the
device from SLEEP.
15.3.7
A RESET disables the MSSP module and terminates
the current transfer.
TABLE 15-2:
DS39541A-page 158
Legend: x = unknown, u = unchanged, - = unimplemented, read as '0'.
SSPSTAT
SSPCON
SSPBUF Synchronous Serial Port Receive Buffer/Transmit Register
INTCON
TRISC
TRISA
Name
PIR1
IPR1
PIE1
Shaded cells are not used by the MSSP in SPI mode.
SLEEP OPERATION
EFFECTS OF A RESET
PORTC Data Direction Register
WCOL
GIEH
Bit 7
SMP
GIE/
—
—
—
—
REGISTERS ASSOCIATED WITH SPI OPERATION
SSPOV SSPEN
PORTA Data Direction Register
PEIE/
ADIE
ADIP
GIEL
ADIF
Bit 6
CKE
TMR0IE INT0IE
RCIE
RCIP
RCIF
Bit 5
D/A
Advance Information
TXIE
TXIP
Bit 4
TXIF
CKP
P
SSPM3
SSPIE
SSPIP
SSPIF
RBIE
Bit 3
S
TMR0IF
CCP1IE
CCP1IP
CCP1IF
SSPM2
15.3.8
Table 15-1 shows the compatibility between the stan-
dard SPI modes and the states of the CKP and CKE
control bits.
TABLE 15-1:
There is also a SMP bit that controls when the data will
be sampled.
Bit 2
R/W
Standard SPI Mode
Terminology
0, 0
0, 1
1, 0
1, 1
TMR2IE TMR1IE
TMR2IP TMR1IP
TMR2IF TMR1IF
SSPM1
INT0IF
BUS MODE COMPATIBILITY
Bit 1
UA
SPI BUS MODES
SSPM0
RBIF
Bit 0
BF
2001 Microchip Technology Inc.
CKP
Control Bits State
0000 000x 0000 000u
-000 0000 -000 0000
-000 0000 -000 0000
-000 0000 -000 0000
1111 1111 1111 1111
xxxx xxxx uuuu uuuu
0000 0000 0000 0000
--11 1111 --11 1111
0000 0000 0000 0000
0
0
1
1
Value on
POR,
BOR
Value on
RESETS
CKE
all other
1
0
1
0
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