PIC18C601-I/PT Microchip Technology, PIC18C601-I/PT Datasheet - Page 247
![IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,TQFP,64PIN,PLASTIC](/photos/6/81/68123/c04-066_pf_sml.jpg)
PIC18C601-I/PT
Manufacturer Part Number
PIC18C601-I/PT
Description
IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,TQFP,64PIN,PLASTIC
Manufacturer
Microchip Technology
Series
PIC® 18Cr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC18C601-IL.pdf
(320 pages)
3.PIC18C601-IL.pdf
(10 pages)
4.PIC18C601-IL.pdf
(10 pages)
Specifications of PIC18C601-I/PT
Rohs Compliant
YES
Core Processor
PIC
Core Size
8-Bit
Speed
25MHz
Connectivity
EBI/EMI, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Number Of I /o
26
Program Memory Type
ROMless
Ram Size
1.5K x 8
Voltage - Supply (vcc/vdd)
4.2 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
64-TFQFP
Processor Series
PIC18C
Core
PIC
Data Bus Width
8 bit
Program Memory Size
256 KB
Data Ram Size
1.5 KB
Interface Type
3-Wire, I2C, SPI, USART
Maximum Clock Frequency
25 MHz
Number Of Programmable I/os
26
Number Of Timers
4
Operating Supply Voltage
2 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
DV164005, ICE4000, DV164136
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
Details
Other names
PIC18C601I/PT
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC18C601-I/PT
Manufacturer:
MICROCHIP
Quantity:
12 000
Company:
Part Number:
PIC18C601-I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
- PIC16F616T-ISL PDF datasheet
- PIC18C601-IL PDF datasheet #2
- PIC18C601-IL PDF datasheet #3
- PIC18C601-IL PDF datasheet #4
- Current page: 247 of 320
- Download datasheet (6Mb)
RETURN
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Q Cycle Activity:
Example:
2001 Microchip Technology Inc.
After Call
Before Instruction
After Instruction
operation
Decode
No
PC
WRG
STATUS =
BSR
WREG
STATUS =
BSR
PC
Q1
=
=
=
=
=
=
operation
operation
Return from Subroutine
[ label ]
s
(TOS)
if s = 1
(WS)
(STATUSS)
(BSRS)
PCLATU, PCLATH are unchanged
None
Return from subroutine. The stack
is popped and the top of the stack
(TOS) is loaded into the program
counter. If ’s’ = 1, the contents of
the shadow registers WS, STA-
TUSS and BSRS are loaded into
their corresponding registers,
WREG, STATUS and BSR. If
’s’ = 0, no update of these
registers occurs (default).
1
2
RETURN
RETURN FAST
0000
No
No
Q2
TOS
04h
00h
00h
04h
00h
00h
TOS
[0,1]
W,
PC,
RETURN [s]
0000
BSR,
operation
Process
Data
No
STATUS,
Q3
0001
from stack
Advance Information
operation
Pop PC
No
Q4
001s
RLCF
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Q Cycle Activity:
Example:
Before Instruction
After Instruction
Decode
REG
C
N
Z
REG
WREG
C
N
Z
Q1
PIC18C601/801
=
=
=
=
=
=
=
=
=
register ’f’
Rotate Left f through Carry
[ label ] RLCF
0
d
a
(f<n>)
(f<7>)
(C)
C,N,Z
The contents of register 'f' are
rotated one bit to the left through the
Carry Flag. If 'd' is 0 the result is
placed in WREG. If 'd' is 1 the result
is stored back in register 'f' (default).
If ’a’ is 0, the Access Bank will be
selected, overriding the BSR value.
If ’a’ is 1, the Bank will be selected
as per the BSR value.
1
1
RLCF
Read
Q2
0011
1110 0110
0
?
?
1110 0110
1100 1100
1
1
0
f
[0,1]
[0,1]
C
dest<0>
255
dest<n+1>,
C,
01da
Process
REG, W
Data
Q3
register f
DS39541A-page 247
f [,d [,a]]
ffff
destination
Write to
Q4
ffff
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