PIC18C601-I/PT Microchip Technology, PIC18C601-I/PT Datasheet - Page 210
![IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,TQFP,64PIN,PLASTIC](/photos/6/81/68123/c04-066_pf_sml.jpg)
PIC18C601-I/PT
Manufacturer Part Number
PIC18C601-I/PT
Description
IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,TQFP,64PIN,PLASTIC
Manufacturer
Microchip Technology
Series
PIC® 18Cr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC18C601-IL.pdf
(320 pages)
3.PIC18C601-IL.pdf
(10 pages)
4.PIC18C601-IL.pdf
(10 pages)
Specifications of PIC18C601-I/PT
Rohs Compliant
YES
Core Processor
PIC
Core Size
8-Bit
Speed
25MHz
Connectivity
EBI/EMI, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Number Of I /o
26
Program Memory Type
ROMless
Ram Size
1.5K x 8
Voltage - Supply (vcc/vdd)
4.2 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
64-TFQFP
Processor Series
PIC18C
Core
PIC
Data Bus Width
8 bit
Program Memory Size
256 KB
Data Ram Size
1.5 KB
Interface Type
3-Wire, I2C, SPI, USART
Maximum Clock Frequency
25 MHz
Number Of Programmable I/os
26
Number Of Timers
4
Operating Supply Voltage
2 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
DV164005, ICE4000, DV164136
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
Details
Other names
PIC18C601I/PT
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC18C601-I/PT
Manufacturer:
MICROCHIP
Quantity:
12 000
Company:
Part Number:
PIC18C601-I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
- PIC16F616T-ISL PDF datasheet
- PIC18C601-IL PDF datasheet #2
- PIC18C601-IL PDF datasheet #3
- PIC18C601-IL PDF datasheet #4
- Current page: 210 of 320
- Download datasheet (6Mb)
PIC18C601/801
19.2
The Watchdog Timer is a free running on-chip RC oscil-
lator, which does not require any external components.
This RC oscillator is separate from the RC oscillator of
the OSC1/CLKI pin. That means that the WDT will run,
even if the clock on the OSC1/CLKI and OSC2/CLKO
pins of the device has been stopped; for example, by
execution of a SLEEP instruction.
During normal operation, a WDT time-out generates a
device RESET (Watchdog Timer Reset). If the device is
in SLEEP mode, a WDT time-out causes the device to
wake-up and continue with normal operation (Watch-
dog Timer Wake-up). The TO bit in the RCON register
will be cleared upon a WDT time-out.
By default, the Watchdog Timer is disabled by configu-
ration to allow software control over Watchdog Timer
operation. If the WDT is enabled by configuration, soft-
ware execution may not disable this function. When the
Watchdog Timer is disabled by configuration, the
SWDTEN bit in the WDTCON register enables/
disables the operation of the WDT.
REGISTER 19-5:
DS39541A-page 210
Watchdog Timer (WDT)
bit 7-4
bit 3-1
bit 0
WDTCON REGISTER
bit 7
Unimplemented: Read as ’0’
SWDPS2:SWDPS0: Software Watchdog Timer Postscale Select bits
111 = 1:128
110 = 1:64
101 = 1:32
100 = 1:16
011 = 1:8
010 = 1:4
001 = 1:2
000 = 1:1
SWDTEN: Software Controlled Watchdog Timer Enable bit
1 = Watchdog Timer is on
0 = Watchdog Timer is turned off if it is not disabled
Legend:
R = Readable bit
- n = Value at POR
U-0
—
U-0
—
Advance Information
U-0
—
W = Writable bit
’1’ = Bit is set
U-0
—
The WDT time-out period values may be found in the
Electrical Specifications section under parameter #31.
Values for the WDT postscaler may be assigned by
using configuration bits WDPS<3:1> in CONFIG2H
register. If the Watchdog Timer is disabled by configu-
ration, values for the WDT postscaler may be assigned
using the SWDPS bits in the WDTCON register.
19.2.1
Register 19-5 shows the WDTCON register. This is a
readable and writable register. It contains control bits to
control the Watchdog Timer from user software. If the
Watchdog Timer is enabled by configuration, this regis-
ter setting is ignored.
Note 1: The CLRWDT and SLEEP instructions
SWDPS2
2: When a CLRWDT instruction is executed
R/W-0
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared
CONTROL REGISTER
clear the WDT and the postscaler, if
assigned to the WDT, and prevent it from
timing out and generating a device
RESET condition.
and the prescaler is assigned to the WDT,
the prescaler count will be cleared, but
the prescaler assignment is not changed.
SWDPS1 SWDPS0 SWDTEN
R/W-0
2001 Microchip Technology Inc.
x = Bit is unknown
R/W-0
R/W-0
bit 0
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