PIC18LF4480-I/P Microchip Technology, PIC18LF4480-I/P Datasheet - Page 169
![IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,DIP,40PIN,PLASTIC](/photos/6/61/66192/150-40-dip_sml.jpg)
PIC18LF4480-I/P
Manufacturer Part Number
PIC18LF4480-I/P
Description
IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,DIP,40PIN,PLASTIC
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC18F2221-ISO.pdf
(46 pages)
3.PIC18F4480-IPT.pdf
(490 pages)
4.PIC18LF2480-ISP.pdf
(14 pages)
Specifications of PIC18LF4480-I/P
Rohs Compliant
YES
Core Processor
PIC
Core Size
8-Bit
Speed
40MHz
Connectivity
CAN, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, HLVD, POR, PWM, WDT
Number Of I /o
36
Program Memory Size
16KB (8K x 16)
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
768 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Data Converters
A/D 11x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
40-DIP (0.600", 15.24mm)
Processor Series
PIC18LF
Core
PIC
Data Bus Width
8 bit
Data Ram Size
768 B
Interface Type
SPI, I2C, EUSART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
25
Number Of Timers
4
Maximum Operating Temperature
+ 85 C
Mounting Style
Through Hole
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DV164136, DM163011
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 11 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC18LF4480-I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
- PIC16F616T-ISL PDF datasheet
- PIC18F2221-ISO PDF datasheet #2
- PIC18F4480-IPT PDF datasheet #3
- PIC18LF2480-ISP PDF datasheet #4
- Current page: 169 of 490
- Download datasheet (9Mb)
16.2
In Capture mode, the CCPR1H:CCPR1L register pair
captures the 16-bit value of the TMR1 or TMR3 regis-
ters when an event occurs on the CCP1 pin (RB3 or
RC1, depending on device configuration). An event is
defined as one of the following:
• every falling edge
• every rising edge
• every 4th rising edge
• every 16th rising edge
The event is selected by the mode select bits,
CCP1M<3:0> (CCP1CON<3:0>). When a capture is
made, the interrupt request flag bit, CCP1IF (PIR2<1>),
is set; it must be cleared in software. If another capture
occurs before the value in register CCPR1 is read, the
old captured value is overwritten by the new captured
value.
16.2.1
In Capture mode, the appropriate CCP1/ECCP1 pin
should be configured as an input by setting the
corresponding TRIS direction bit.
16.2.2
The timers that are to be used with the capture feature
(Timer1 and/or Timer3) must be running in Timer mode
or Synchronized Counter mode. In Asynchronous
Counter mode, the capture operation may not work.
The timer to be used with each CCP module is selected
in the T3CON register (see Section 16.1.1 “CCP
Modules and Timer Resources”).
16.2.3
When the Capture mode is changed, a false capture
interrupt may be generated. The user should keep the
CCPxIE interrupt enable bit clear to avoid false inter-
rupts. The interrupt flag bit, CCPxIF, should also be
cleared following any such change in operating mode.
© 2009 Microchip Technology Inc.
Note:
Capture Mode
CCP1/ECCP1 PIN CONFIGURATION
If RC2/CCP1 or RD4/PSP4/ECCP1/P1A
is configured as an output, a write to the
port can cause a capture condition.
TIMER1/TIMER3 MODE SELECTION
SOFTWARE INTERRUPT
PIC18F2480/2580/4480/4580
16.2.4
There are four prescaler settings in Capture mode; they
are specified as part of the operating mode selected by
the mode select bits (CCP1M<3:0>). Whenever the
CCP module is turned off or the CCP module is not in
Capture mode, the prescaler counter is cleared. This
means that any Reset will clear the prescaler counter.
Switching from one capture prescaler to another may
generate an interrupt. Also, the prescaler counter will
not be cleared; therefore, the first capture may be from
a non-zero prescaler. Example 16-1 shows the recom-
mended method for switching between capture
prescalers. This example also clears the prescaler
counter and will not generate the “false” interrupt.
16.2.5
The CAN capture event occurs when a message is
received in any of the receive buffers. When config-
ured, the CAN module provides the trigger to the CCP1
module to cause a capture event. This feature is
provided to “time-stamp” the received CAN messages.
This feature is enabled by setting the CANCAP bit of
the CAN I/O Control register (CIOCON<4>). The
message receive signal from the CAN module then
takes the place of the events on RC2/CCP1.
If this feature is selected, then four different capture
options for CCP1M<3:0> are available:
• 0100 – every time a CAN message is received
• 0101 – every time a CAN message is received
• 0110 – every 4th time a CAN message is
• 0111 – capture mode, every 16th time a CAN
EXAMPLE 16-1:
CLRF
MOVLW
MOVWF
CCP1CON
NEW_CAPT_PS ; Load WREG with the
CCP1CON
message is received
received
CCP PRESCALER
CAN MESSAGE TIME-STAMP
CHANGING BETWEEN
CAPTURE PRESCALERS
; Turn CCP module off
; new prescaler mode
; value and CCP ON
; Load CCP1CON with
; this value
DS39637D-page 169
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