PIC18LF4480-I/P Microchip Technology, PIC18LF4480-I/P Datasheet - Page 332
![IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,DIP,40PIN,PLASTIC](/photos/6/61/66192/150-40-dip_sml.jpg)
PIC18LF4480-I/P
Manufacturer Part Number
PIC18LF4480-I/P
Description
IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,DIP,40PIN,PLASTIC
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC18F2221-ISO.pdf
(46 pages)
3.PIC18F4480-IPT.pdf
(490 pages)
4.PIC18LF2480-ISP.pdf
(14 pages)
Specifications of PIC18LF4480-I/P
Rohs Compliant
YES
Core Processor
PIC
Core Size
8-Bit
Speed
40MHz
Connectivity
CAN, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, HLVD, POR, PWM, WDT
Number Of I /o
36
Program Memory Size
16KB (8K x 16)
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
768 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Data Converters
A/D 11x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
40-DIP (0.600", 15.24mm)
Processor Series
PIC18LF
Core
PIC
Data Bus Width
8 bit
Data Ram Size
768 B
Interface Type
SPI, I2C, EUSART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
25
Number Of Timers
4
Maximum Operating Temperature
+ 85 C
Mounting Style
Through Hole
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DV164136, DM163011
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 11 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC18LF4480-I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
- PIC16F616T-ISL PDF datasheet
- PIC18F2221-ISO PDF datasheet #2
- PIC18F4480-IPT PDF datasheet #3
- PIC18LF2480-ISP PDF datasheet #4
- Current page: 332 of 490
- Download datasheet (9Mb)
PIC18F2480/2580/4480/4580
24.4.3
In Mode 2, two or more receive buffers are used to form
the receive FIFO (first in, first out) buffer. There is no
one-to-one relationship between the receive buffer and
acceptance filter registers. Any filter that is enabled and
linked to any FIFO receive buffer can generate
acceptance and cause FIFO to be updated.
FIFO length is user-programmable, from 2-8 buffers
deep. FIFO length is determined by the very first pro-
grammable buffer that is configured as a transmit buf-
fer. For example, if Buffer 2 (B2) is programmed as a
transmit buffer, FIFO consists of RXB0, RXB1, B0 and
B1 – creating a FIFO length of 4. If all programmable
buffers are configured as receive buffers, FIFO will
have the maximum length of 8.
The following is the list of resources available in Mode 2:
• Three transmit buffers: TXB0, TXB1 and TXB2
• Two receive buffers: RXB0 and RXB1
• Six buffers programmable as TX or RX; receive
• Automatic RTR handling on B0-B5
• Sixteen acceptance filters: RXF0-RXF15
• Two dedicated acceptance mask registers;
• Programmable data filter on standard identifier
24.5
24.5.1
The PIC18F2480/2580/4480/4580 devices implement
three dedicated transmit buffers – TXB0, TXB1 and
TXB2. Each of these buffers occupies 14 bytes of
SRAM and are mapped into the SFR memory map.
These are the only transmit buffers available in
Mode 0. Mode 1 and 2 may access these and other
additional buffers.
Each transmit buffer contains one Control register
(TXBnCON), four Identifier registers (TXBnSIDL,
TXBnSIDH, TXBnEIDL, TXBnEIDH), one Data Length
Count register (TXBnDLC) and eight Data Byte
registers (TXBnDm).
24.5.2
The PIC18F2480/2580/4480/4580 devices implement
two dedicated receive buffers: RXB0 and RXB1. Each
of these buffers occupies 14 bytes of SRAM and are
mapped into SFR memory map. These are the only
receive buffers available in Mode 0. Mode 1 and 2 may
access these and other additional buffers.
DS39637D-page 332
buffers form FIFO: B0-B5
RXF15 programmable as third mask:
RXM0-RXM1, RXF15
messages: SDFLC, useful for DeviceNet protocol
CAN Message Buffers
MODE 2 – ENHANCED FIFO MODE
DEDICATED TRANSMIT BUFFERS
DEDICATED RECEIVE BUFFERS
Each receive buffer contains one Control register
(RXBnCON), four Identifier registers (RXBnSIDL,
RXBnSIDH, RXBnEIDL, RXBnEIDH), one Data Length
Count register (RXBnDLC) and eight Data Byte
registers (RXBnDm).
There is also a separate Message Assembly Buffer
(MAB) which acts as an additional receive buffer. MAB
is always committed to receiving the next message
from the bus and is not directly accessible to user firm-
ware. The MAB assembles all incoming messages one
by one. A message is transferred to appropriate
receive buffers only if the corresponding acceptance
filter criteria is met.
24.5.3
The ECAN module implements six new buffers: B0-B5.
These buffers are individually programmable as either
transmit or receive buffers. These buffers are available
only in Mode 1 and 2. As with dedicated transmit and
receive buffers, each of these programmable buffers
occupies 14 bytes of SRAM and are mapped into SFR
memory map.
Each buffer contains one Control register (BnCON),
four Identifier registers (BnSIDL, BnSIDH, BnEIDL,
BnEIDH), one Data Length Count register (BnDLC)
and eight Data Byte registers (BnDm). Each of these
registers contains two sets of control bits. Depending
on whether the buffer is configured as transmit or
receive, one would use the corresponding control bit
set. By default, all buffers are configured as receive
buffers. Each buffer can be individually configured as a
transmit or receive buffer by setting the corresponding
TXENn bit in the BSEL0 register.
When configured as transmit buffers, user firmware
may access transmit buffers in any order similar to
accessing dedicated transmit buffers. In receive
configuration with Mode 1 enabled, user firmware may
also access receive buffers in any order required. But
in Mode 2, all receive buffers are combined to form a
single FIFO. Actual FIFO length is programmable by
user firmware. Access to FIFO must be done through
the FIFO Pointer bits (FP<4:0>) in the CANCON
register. It must be noted that there is no hardware
protection against out of order FIFO reads.
PROGRAMMABLE TRANSMIT/
RECEIVE BUFFERS
© 2009 Microchip Technology Inc.
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