PIC18LF4480-I/P Microchip Technology, PIC18LF4480-I/P Datasheet - Page 385
![IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,DIP,40PIN,PLASTIC](/photos/6/61/66192/150-40-dip_sml.jpg)
PIC18LF4480-I/P
Manufacturer Part Number
PIC18LF4480-I/P
Description
IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,DIP,40PIN,PLASTIC
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC18F2221-ISO.pdf
(46 pages)
3.PIC18F4480-IPT.pdf
(490 pages)
4.PIC18LF2480-ISP.pdf
(14 pages)
Specifications of PIC18LF4480-I/P
Rohs Compliant
YES
Core Processor
PIC
Core Size
8-Bit
Speed
40MHz
Connectivity
CAN, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, HLVD, POR, PWM, WDT
Number Of I /o
36
Program Memory Size
16KB (8K x 16)
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
768 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Data Converters
A/D 11x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
40-DIP (0.600", 15.24mm)
Processor Series
PIC18LF
Core
PIC
Data Bus Width
8 bit
Data Ram Size
768 B
Interface Type
SPI, I2C, EUSART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
25
Number Of Timers
4
Maximum Operating Temperature
+ 85 C
Mounting Style
Through Hole
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DV164136, DM163011
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 11 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC18LF4480-I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
- PIC16F616T-ISL PDF datasheet
- PIC18F2221-ISO PDF datasheet #2
- PIC18F4480-IPT PDF datasheet #3
- PIC18LF2480-ISP PDF datasheet #4
- Current page: 385 of 490
- Download datasheet (9Mb)
CPFSGT
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
© 2009 Microchip Technology Inc.
Q Cycle Activity:
If skip:
If skip and followed by 2-word instruction:
Before Instruction
After Instruction
operation
operation
operation
Decode
No
No
No
PC
W
If REG
If REG
Q1
Q1
Q1
PC
PC
register ‘f’
operation
operation
operation
Compare f with W, Skip if f > W
CPFSGT
0 ≤ f ≤ 255
a ∈ [0,1]
(f) − (W),
skip if (f) > (W)
(unsigned comparison)
None
Compares the contents of data memory
location ‘f’ to the contents of the W by
performing an unsigned subtraction.
If the contents of ‘f’ are greater than the
contents of WREG, then the fetched
instruction is discarded and a NOP is
executed instead, making this a
two-cycle instruction.
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank.
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f ≤ 95 (5Fh). See
Section 26.2.3 “Byte-Oriented and
Bit-Oriented Instructions in Indexed
Literal Offset Mode” for details.
1
1(2)
Note:
HERE
NGREATER
GREATER
Read
0110
No
No
No
Q2
Q2
Q2
=
=
>
=
≤
=
3 cycles if skip and followed
by a 2-word instruction.
Address (HERE)
?
W;
Address (GREATER)
W;
Address (NGREATER)
f {,a}
010a
operation
operation
operation
CPFSGT REG, 0
:
:
Process
Data
No
No
No
Q3
Q3
Q3
ffff
operation
operation
operation
operation
PIC18F2480/2580/4480/4580
No
No
No
No
Q4
Q4
Q4
ffff
CPFSLT
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
Q Cycle Activity:
If skip:
If skip and followed by 2-word instruction:
Before Instruction
After Instruction
operation
operation
operation
Decode
No
No
No
PC
W
If REG
PC
If REG
PC
Q1
Q1
Q1
register ‘f’
operation
operation
operation
Compare f with W, Skip if f < W
CPFSLT
0 ≤ f ≤ 255
a ∈ [0,1]
(f) – (W),
skip if (f) < (W)
(unsigned comparison)
None
Compares the contents of data memory
location ‘f’ to the contents of W by
performing an unsigned subtraction.
If the contents of ‘f’ are less than the
contents of W, then the fetched
instruction is discarded and a NOP is
executed instead, making this a
two-cycle instruction.
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank.
1
1(2)
Note:
HERE
NLESS
LESS
Read
0110
No
No
No
Q2
Q2
Q2
=
=
<
=
≥
=
3 cycles if skip and followed
by a 2-word instruction.
Address (HERE)
?
W;
Address (LESS)
W;
Address (NLESS)
CPFSLT REG, 1
:
:
f {,a}
000a
operation
operation
operation
Process
Data
No
No
No
Q3
Q3
Q3
DS39637D-page 385
ffff
operation
operation
operation
operation
No
No
No
No
Q4
Q4
Q4
ffff
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