PIC18LF6310T-I/PT Microchip Technology, PIC18LF6310T-I/PT Datasheet - Page 138
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PIC18LF6310T-I/PT
Manufacturer Part Number
PIC18LF6310T-I/PT
Description
IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,TQFP,64PIN,PLASTIC
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Specifications of PIC18LF6310T-I/PT
Rohs Compliant
YES
Core Processor
PIC
Core Size
8-Bit
Speed
40MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, HLVD, POR, PWM, WDT
Number Of I /o
54
Program Memory Size
8KB (4K x 16)
Program Memory Type
FLASH
Ram Size
768 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-TFQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC18LF6310T-I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
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PIC18F6310/6410/8310/8410
TABLE 11-9:
DS39635C-page 138
RE0/AD8/RD
RE1/AD9/WR
RE2/AD10/CS
RE3/AD11
RE4/AD12
RE5/AD13
RE6/AD14
RE7/CCP2/AD15
Legend:
Note 1:
Pin Name
2:
3:
O = Output, I = Input, DIG = Digital Output, ST = Schmitt Buffer Input, TTL = TTL Buffer Input,
x = Don’t care (TRIS bit does not affect port direction or is overridden for this option).
Alternate assignment for CCP2 when CCP2MX Configuration bit is cleared (all devices in Microcontroller mode).
External memory interface I/O takes priority over all other digital and PSP I/O.
Implemented on 80-pin devices only.
Function
PORTE FUNCTIONS
CCP2
AD10
AD11
AD12
AD13
AD14
AD15
AD8
AD9
RE0
RE1
RE2
RE3
RE4
RE5
RE6
RE7
WR
RD
CS
(3)
(3)
(3)
(3)
(3)
(3)
(3)
(3)
(1)
Setting
TRIS
0
1
x
x
1
0
1
x
x
1
0
1
x
x
1
0
1
x
x
0
1
x
x
0
1
x
x
0
1
x
x
0
1
0
1
x
x
I/O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
Type
DIG
DIG
TTL
TTL
DIG
DIG
TTL
TTL
DIG
DIG
TTL
TTL
DIG
DIG
TTL
DIG
DIG
TTL
DIG
DIG
TTL
DIG
DIG
TTL
DIG
DIG
DIG
TTL
I/O
ST
ST
ST
ST
ST
ST
ST
ST
ST
LATE<0> data output.
PORTE<0> data input.
External memory interface, Address/Data Bit 8 output.
External memory interface, Data Bit 8 input.
Parallel Slave Port read enable control input.
LATE<1> data output.
PORTE<1> data input.
External memory interface, Address/Data Bit 9 output.
External memory interface, Data Bit 9 input.
Parallel Slave Port write enable control input.
LATE<2> data output.
PORTE<2> data input.
External memory interface, Address/Data Bit 10 output.
External memory interface, Data Bit 10 input.
Parallel Slave Port chip select control input.
LATE<3> data output.
PORTE<3> data input.
External memory interface, Address/Data Bit 11 output.
External memory interface, Data Bit 11 input.
LATE<4> data output.
PORTE<4> data input.
External memory interface, Address/Data Bit 12 output.
External memory interface, Data Bit 12 input.
LATE<5> data output.
PORTE<5> data input.
External memory interface, Address/Data Bit 13 output.
External memory interface, Data Bit 13 input.
LATE<6> data output.
PORTE<6> data input.
External memory interface, Address/Data Bit 14 output.
External memory interface, Data Bit 14 input.
LATE<7> data output.
PORTE<7> data input.
CCP2 compare output and CCP2 PWM output; takes priority over port data.
CCP2 capture input.
External memory interface, Address/Data Bit 15 output.
External memory interface, Data Bit 15 input.
Description
2010 Microchip Technology Inc.
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
(2)
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