PIC18LF6310T-I/PT Microchip Technology, PIC18LF6310T-I/PT Datasheet - Page 174
![IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,TQFP,64PIN,PLASTIC](/photos/6/81/68123/c04-066_pf_sml.jpg)
PIC18LF6310T-I/PT
Manufacturer Part Number
PIC18LF6310T-I/PT
Description
IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,TQFP,64PIN,PLASTIC
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Specifications of PIC18LF6310T-I/PT
Rohs Compliant
YES
Core Processor
PIC
Core Size
8-Bit
Speed
40MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, HLVD, POR, PWM, WDT
Number Of I /o
54
Program Memory Size
8KB (4K x 16)
Program Memory Type
FLASH
Ram Size
768 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-TFQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC18LF6310T-I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
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PIC18F6310/6410/8310/8410
16.4.2
The PWM duty cycle is specified by writing to the
CCPR2L register and to the CCP2CON<5:4> bits. Up
to 10-bit resolution is available. The CCPR2L contains
the eight MSbs and the CCP2CON<5:4> contains the
two LSbs. This 10-bit value is represented by
CCPR2L:CCP2CON<5:4>. The following equation is
used to calculate the PWM duty cycle in time:
EQUATION 16-2:
CCPR2L and CCP2CON<5:4> can be written to at any
time, but the duty cycle value is not latched into
CCPR2H until after a match between PR2 and TMR2
occurs (i.e., the period is complete). In PWM mode,
CCPR2H is a read-only register.
The CCPR2H register and a 2-bit internal latch are
used to double-buffer the PWM duty cycle. This
double-buffering is essential for glitchless PWM
operation.
When the CCPR2H and 2-bit latch match TMR2,
concatenated with an internal 2-bit Q clock or 2 bits of
the TMR2 prescaler, the CCP2 pin is cleared.
TABLE 16-3:
DS39635C-page 174
Timer Prescaler (1, 4, 16)
PR2 Value
Maximum Resolution (bits)
PWM Duty Cycle = (CCPR2L:CCP2CON<5:4>) •
PWM Frequency
PWM DUTY CYCLE
EXAMPLE PWM FREQUENCIES AND RESOLUTIONS AT 40 MHz
T
OSC
• (TMR2 Prescale Value)
2.44 kHz
FFh
16
10
9.77 kHz
FFh
10
4
39.06 kHz
The maximum PWM resolution (bits) for a given PWM
frequency is given by the equation:
EQUATION 16-3:
16.4.3
The following steps should be taken when configuring
the CCP module for PWM operation:
1.
2.
3.
4.
5.
Note:
FFh
10
1
Set the PWM period by writing to the PR2
register.
Set the PWM duty cycle by writing to the
CCPR2L register and CCP2CON<5:4> bits.
Make the CCP2 pin an output by clearing the
appropriate TRIS bit.
Set the TMR2 prescale value, then enable
Timer2 by writing to T2CON.
Configure the CCP2 module for PWM operation.
PWM Resolution (max)
If the PWM duty cycle value is longer than
the PWM period, the CCP2 pin will not be
cleared.
SETUP FOR PWM OPERATION
156.25 kHz
3Fh
1
8
2010 Microchip Technology Inc.
312.50 kHz
=
1Fh
log
-----------------------------bits
1
7
log
---------------
F
F
PWM
2
OSC
416.67 kHz
6.58
17h
1
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