PIC18LF6310T-I/PT Microchip Technology, PIC18LF6310T-I/PT Datasheet - Page 98
![IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,TQFP,64PIN,PLASTIC](/photos/6/81/68123/c04-066_pf_sml.jpg)
PIC18LF6310T-I/PT
Manufacturer Part Number
PIC18LF6310T-I/PT
Description
IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,TQFP,64PIN,PLASTIC
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Specifications of PIC18LF6310T-I/PT
Rohs Compliant
YES
Core Processor
PIC
Core Size
8-Bit
Speed
40MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, HLVD, POR, PWM, WDT
Number Of I /o
54
Program Memory Size
8KB (4K x 16)
Program Memory Type
FLASH
Ram Size
768 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-TFQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC18LF6310T-I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
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PIC18F6310/6410/8310/8410
8.2.2
Figure 8-2
mode for PIC18F8410 devices. This mode is used for
word-wide memories, which includes some of the
EPROM and Flash type memories. This mode allows
opcode fetches and table reads from all forms of 16-bit
memory and table writes to any type of word-wide
external memories. This method makes a distinction
between TBLWT cycles to even or odd addresses.
During a TBLWT cycle to an even address
(TBLPTR<0> = 0), the TABLAT data is transferred to a
holding latch and the external address data bus is
tri-stated for the data portion of the bus cycle. No write
signals are activated.
FIGURE 8-2:
DS39635C-page 98
Note 1:
shows an example of 16-Bit Word Write
16-BIT WORD WRITE MODE
PIC18F8410
AD<15:8>
A<19:16>
This signal only applies to table writes. See
AD<7:0>
16-BIT WORD WRITE MODE EXAMPLE
WRH
ALE
CE
OE
373
373
Section 7.1 “Table Reads and Table
During
(TBLPTR<0> = 1), the TABLAT data is presented on
the upper byte of the AD<15:0> bus. The contents of
the holding latch are presented on the lower byte of the
AD<15:0> bus.
The WRH signal is strobed for each write cycle; the
WRL pin is unused. The signal on the BA0 pin indicates
the LSb of TBLPTR, but it is left unconnected. Instead,
the UB and LB signals are active to select both bytes.
The obvious limitation to this method is that the table
write must be done in pairs on a specific word boundary
to correctly write a word location.
A<20:1>
D<15:0>
a
TBLWT
Address Bus
Data Bus
Control Lines
D<15:0>
A<x:0>
cycle
2010 Microchip Technology Inc.
CE
Writes”.
EPROM Memory
to
OE
JEDEC Word
an
WR
odd
(1)
address
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