EVAL-ADF4360-7EBZ1 Analog Devices Inc, EVAL-ADF4360-7EBZ1 Datasheet - Page 17

• Manufacturer Part Number: EVAL-ADF4360-7EBZ1
• Description: PLL/Frequency Synthesizer EVAL BOARD
• Manufacturer: Analog Devices Inc

Specifications of EVAL-ADF4360-7EBZ1

• Silicon Manufacturer: Analog Devices
• Application Sub Type: Integer-N Synthesizer
• Kit Application Type: Clock & Timing
• Silicon Core Number: ADF4360-7
• Kit Contents: Board
• Main Purpose: Timing, Frequency Synthesizer
• Embedded: No
• Utilized Ic / Part: ADF4360-7
• Primary Attributes: Single Integer-N PLL with VCO
• Secondary Attributes: 900MHz, 200kHz PFD
• Frequency: 1.8GHz
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: EVAL-ADF4360-7EB1; EVAL-ADF4360-7EB1; Q5173330; Q5652985

POWER-UP
Power-Up Sequence
The correct programming sequence for the ADF4360-7 after
power-up is:
1. R counter latch
2. Control latch
3. N counter latch
Initial Power-Up
Initial power-up refers to programming the part after the
application of voltage to the AV
initial power-up, an interval is required between programming
the control latch and programming the N counter latch. This
interval is necessary to allow the transient behavior of the
ADF4360-7 during initial power-up to settle.
Table 10. C
C
10 µF
440 nF
N
Value
N
Recommended Interval Between
Control Latch and N Counter Latch
≥10 ms
≥ 600 µs
Capacitance vs. Interval and Phase Noise
POWER-UP
CLOCK
DATA
LE
DD
, DV
DD
LATCH DATA
R COUNTER
, V
VCO
and CE pins. On
Open-Loop Phase Noise @ 10 kHz
Offset (L1 and L2 = 1.0 nH)
−90 dBc
−88 dBc
Figure 22. ADF4360-7 Power-Up Timing
LATCH DATA
Rev. A | Page 17 of 28
CONTROL
During initial power-up, a write to the control latch powers up
the part, and the bias currents of the VCO begin to settle. If
these currents have not settled to within 10% of their steady-
state value, and if the N counter latch is then programmed, the
VCO may not oscillate at the desired frequency, which does not
allow the band select logic to choose the correct frequency
band, and the ADF4360-7 may not achieve lock. If the recom-
mended interval is inserted, and the N counter latch is pro-
grammed, the band select logic can choose the correct fre-
quency band, and the part locks to the correct frequency.
The duration of this interval is affected by the value of the
capacitor on the C
reduce the close-in noise of the ADF4360-7 VCO. The
recommended value of this capacitor is 10 µF. Using this value
requires an interval of ≥10 ms between the latching in of the
control latch bits and latching in of the N counter latch bits. If a
shorter delay is required, the capacitor can be reduced. A slight
phase noise penalty is incurred by this change, which is further
explained in the Table 10.
CONTROL LATCH WRITE TO
N COUNTER LATCH WRITE
REQUIRED INTERVAL
Open-Loop Phase Noise @ 10 kHz
Offset (L1 and L2 = 13.0 nH)
−99 dBc
−97 dBc
N
pin (Pin 14). This capacitor is used to
LATCH DATA
N COUNTER
ADF4360-7