5XX MOTHERBOARD ONLY AXIOM, 5XX MOTHERBOARD ONLY Datasheet - Page 12

• Manufacturer Part Number: 5XX MOTHERBOARD ONLY
• Description: CMD-5XX MOTHERBOARD ONLY
• Manufacturer: AXIOM

Specifications of 5XX MOTHERBOARD ONLY

• Silicon Manufacturer: Freescale
• Core Architecture: Power
• Core Sub-architecture: PowerPC
• Features: Plug And Play, Axiom Monitor, Communication Interfaces, Keypad And LCD Module Support
• Kit Contents: Board
• Silicon Core Number: MPC555, MPC556, MPC561
• Silicon Family Name: MPC5xx

Memory Device / Bank Selection and Configuration.
The CMD-5xx board has three external memory banks and a PRU that provide:
Each memory bank can be configured individually to operate from the MPC5xx chip selects. Caution should be used not to place
more than one memory bank on the same chip select or properly configure the chip select to operate the Memory Devices in the
memory bank correctly. Failure to observe precautions may render the external memory bus inoperable and cause the user
great anxiety and grief.
The MAP Switch, MEM_EN option jumper, and PRU_EN option jumper connect MPC5xx chip selects to the different memory
banks. If memory access problems occur, the settings of these options and the associated chip select configurations should be
reviewed with some detail. Information to configure the chip selects and memory is detailed in the following sections.
Memory Bank Chip Select Configuration
Application software that executes on reset must configure each memory bank chip select properly for correct operation. Following
is a reference table of Memory Bank chip select values:
MEM Sockets - 16 bit port
MEM Sockets - 8-bit port
MEM Sockets
RAM – 32 bit port only
RAM – asynchronous mode
RAM – burst mode
Flash – 32 bit port asynchronous
Flash – 16 bit port asynchronous
Flash – 32 bit port asynchronous
Flash – 32 bit port burst mode
Flash – 16 bit port burst mode
PRU – 32 bit asynchronous only
PRU – External terminate
MAP_SW – Ram Bank and Flash Bank Options
The MAP Switch provides chip select to memory bank selection for the Synchronous RAM Memory Bank and the Burstable Flash
Memory Bank. Positions 1-4 set the Chip Select for RAM, the rest are for Flash. Position 8 determines the Flash Bank Port Size so
that either 16 or 32 bit burstable port can be selected. If switches 1 to 7 are all off the RAM and Flash Banks are disabled.
The Default positions shown below will set RAM to CS1 and FLASH to 32 bit mode on CS2.
MAP_SW
Position
1
2
3
4
5
6
7
8
512K x 32bit (2MByte) Synchronous Static RAM (U2 – U5)
1M x 32bit (4MByte) Burstable Flash EEPROM (U13 - U14)
MEM Option Sockets for 8 or 16bit wide EPROM memory (U15 – U16)
Port Replacement Unit (PRU) with LCD and Keypad Ports
Memory Bank
Select
Width
Flash
Chip
CS0
CS1
CS2
CS3
CS0
CS1
CS2
Port
Position
Default
ON
ON
Off
Off
Off
Off
Off
Off
Reg. Default Value
BRO
OR0
ORx
ORx
ORx
ORx
BR0
BRx
BRx
BRx
BRx
RAM – on for BDM use typically (with MEM_EN off)
RAM – *Default monitor operation position
RAM
RAM
Flash – on to Reset (BOOT) from Flash Bank (with MEM_EN off)
Flash
Flash - *D
Flash – Port Width
0xFFC00020
0xFFC00030
0xFFFF80F0
0x00C00003
0x00C00803
0x00400803
0x00400403
0x00800003
0x01000007
0xFFC0000
TBD
efault monitor operation position
Base address = 0x400000, Port width = 16 bit *Default
Port width = 8 bit
Memory Range = 0x400000, wait state = 2, 40MHz / 70ns devices
Base Address = 0x800000, Port width = 32 bit FIXED *Default
Memory Range = 0x400000, wait state = 0 or 1, Note:
asynchronous operation requires 1 wait state no matter clock
frequency on rev. C (CY1339 devices).
TBD
Base address 0xC00000, Port width 32 bit, *Default MAP_SW-8 =
off
Base address 0xC00000, Port width = 16 bit , MAP_SW-8 = on
Memory range = 0x400000, wait state = 3, asynchronous operation
40Mhz clock, 95ns device
Base address = 0x1000000, Port width = 32 bit *Default
Memory Range 0x8000, wait state = External Terminate (TA*)
*Default
Memory Bank Connection and Notes
Off = 32 bit wide port (parallel flash devices),
On = 16 bit wide port (single flash device)
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Notes
CMD-5xx 08/07/02