IPR-PCIE/4 Altera, IPR-PCIE/4 Datasheet - Page 218
IPR-PCIE/4
Manufacturer Part Number
IPR-PCIE/4
Description
IP CORE Renewal Of IP-PCIE/4
Manufacturer
Altera
Type
MegaCorer
Specifications of IPR-PCIE/4
Software Application
IP CORE, Interface And Protocols, PCI
Supported Families
Arria GX, Cyclone II, HardCopy II, Stratix II
Core Architecture
FPGA
Core Sub-architecture
Arria, Cyclone, Stratix
Rohs Compliant
NA
Function
PCI Express Compiler, x4 Link Width
License
Renewal License
Lead Free Status / RoHS Status
na
Lead Free Status / RoHS Status
na
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Configuration Signals for x1 and x4 MegaCore Functions
A–2
PCI Express Compiler User Guide
k_conf[99]
k_conf[100]
k_conf[101]
k_conf[104:102]
k_conf[105]
k_conf[106]
k_conf[107]
k_conf[108]
k_conf[109]
k_conf[110]
k_conf[111]
k_conf[112]
k_conf[115:113]
k_conf[119:116]
k_conf[127:120]
k_conf[130:128]
k_conf[132:131]
k_conf[133]
k_conf[136:134]
Table A–1. Configuration Signals for x1 and x4 MegaCore Functions (Part 2 of 6)
Signal
Fixed to 0
Fixed to 0
Fixed to 0
Fixed to 0
Fixed to 0
Fixed to 0
Fixed to 0
Fixed to 0
Fixed to 0
Fixed to 0
Fixed to 0
Capabilities: Implement
AER
Buffer Setup: Low Priority
Virtual Channels
Fixed to 0b0001
Fixed to 0
Fixed to 0
Fixed to 0
Calculated
Power Management:
Endpoint L0s Acceptable
Latency
Value or Wizard
Page/Label
PCI Express Compiler Version 6.1
Power management capabilities register PME clock
field.
Reserved.
Power management capabilities register device-
specific initialization (DSI) field.
Power management capabilities register maximum
auxiliary current required while in d3cold to support
PME.
Power management capabilities register D1 support
bit.
Power management capabilities register D2 support
bit.
Power management capabilities register PME
message can be sent in D0 state bit.
Power management capabilities register PME
message can be sent in D1 state bit.
Power management capabilities register PME
message can be sent in D2 state bit.
Power management capabilities register PME
message can be sent in D3 hot state bit.
Power management capabilities register PME
message can be sent in D3 cold state bit.
Advanced error reporting capability supported.
Port VC capability register 1 low priority VC field.
Port VC capability register 2 VC arbitration capability
field.
Reserved.
Reserved.
Reserved.
Device capabilities register: extended tag field
supported. Set to 1 when number of tags > 32.
Device capabilities register: endpoint L0s acceptable
latency. 0 = < 64 ns, 1 = 64 - 128 ns, 2 = 128 - 256 ns,
3 = 256 - 512 ns, 4 = 512 ns - 1 μs, 5 = 1 - 2 μs, 6 = 2 -
4 μs, 7 => 4 μs.
Description
Altera Corporation
December 2006
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