IPR-PCIE/4 Altera, IPR-PCIE/4 Datasheet - Page 256
IPR-PCIE/4
Manufacturer Part Number
IPR-PCIE/4
Description
IP CORE Renewal Of IP-PCIE/4
Manufacturer
Altera
Type
MegaCorer
Specifications of IPR-PCIE/4
Software Application
IP CORE, Interface And Protocols, PCI
Supported Families
Arria GX, Cyclone II, HardCopy II, Stratix II
Core Architecture
FPGA
Core Sub-architecture
Arria, Cyclone, Stratix
Rohs Compliant
NA
Function
PCI Express Compiler, x4 Link Width
License
Renewal License
Lead Free Status / RoHS Status
na
Lead Free Status / RoHS Status
na
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Test-In Interface
C–26
PCI Express Compiler User Guide
test_vcselect
Table C–3. test_in Signals (Part 5 of 5)
Signal
TRN
Subblock
31:29
PCI Express Compiler Version 6.1
Bit
Virtual channel test selection. This signal indicates which virtual
channel is currently considered by the test-out interface
(
the select input to a mux that switches a portion of the
bus to output debug signals from different virtual channels (VC).
For example:
●
●
●
●
Certain bits of this signal should be set to 0 to remove unused
logic:
●
●
●
test_out[255:131]
test_vcselect[31:29]:000:test_out[255:131]
describes activity for VC0
test_vcselect[31:29]:001:test_out[255:131]
describes activity for VC1
test_vcselect[31:29]:010:test_out[255:131]
describes activity for VC2
...
1 virtual channel (or signal completely unused): set all three
bits to 000
2 virtual channels: set the 2 MSBs to 00
3 or 4 virtual channels: set the MSB to 0. These bits are
reserved on the x8 MegaCore function.
). This virtual channel test selection is
Description
Altera Corporation
December 2006
test_ou
t
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