IPR-PCIE/4 Altera, IPR-PCIE/4 Datasheet - Page 228
IPR-PCIE/4
Manufacturer Part Number
IPR-PCIE/4
Description
IP CORE Renewal Of IP-PCIE/4
Manufacturer
Altera
Type
MegaCorer
Specifications of IPR-PCIE/4
Software Application
IP CORE, Interface And Protocols, PCI
Supported Families
Arria GX, Cyclone II, HardCopy II, Stratix II
Core Architecture
FPGA
Core Sub-architecture
Arria, Cyclone, Stratix
Rohs Compliant
NA
Function
PCI Express Compiler, x4 Link Width
License
Renewal License
Lead Free Status / RoHS Status
na
Lead Free Status / RoHS Status
na
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Content with Data Payload
Content with
Data Payload
B–2
PCI Express Compiler User Guide
Byte 0
Byte 4
Byte 8
Byte 12 R
Byte 0
Byte 4
Byte 8
Byte 12 Address[31:2]
Byte 0
Byte 4
Byte 8
Byte 12 R
Byte 0
Byte 4
Byte 8
Byte 12 R
Table B–2. Memory Write Request, 32-Bit Addressing
Table B–3. Memory Write Request, 64-Bit Addressing
Table B–4. I/O Write Request
Table B–5. Type 0 Configuration Write Request
+0
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7
0 1 0 0 0 0 0 0 0 TC
Requester ID
Address[31:2]
+0
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7
0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 TD
Requester ID
Address[31:2]
+0
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7
0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 TD EP 0 0 0 0 0 0 0 0 0 0 0 0 0 1
Requester ID
Bus Number
+0
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7
0 1 1 0 0 0 0 0 0 TC
Requester ID
Address[63:32]
Tables B–2
packets with a data payload.
+1
Device Nb.
+1
+1
+1
PCI Express Compiler Version 6.1
through
0 0 0 0 TD EP Attr
0 0 0 0 TD EP Attr
Func
B–9
show the register content for transaction layer
+2
Tag
+2
Tag
+2
Tag
0
+2
Tag
6
6
6
EP 0 0 0 0 0 0 0 0 0 0 0 0 0 1
6
0
5 4 3 2 1 0 7 6 5 4 3 2 1 0
5 4 3 2 1 0 7 6 5 4 3 2 1 0
5 4 3 2 1 0 7 6 5 4 3 2 1 0
0 0 Ext. Reg.
5 4 3 2 1 0 7 6 5 4 3 2 1 0
0 0 Length
0 0 Length
+3
Last BE
+3
+3
0 0 0 0 First BE
+3
0 0 0 0 First BE
Register Nb.
Last BE
Altera Corporation
December 2006
First BE
First BE
0 0
0 0
0 0
0 0
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