CDB5461AU Cirrus Logic Inc, CDB5461AU Datasheet - Page 21

• Manufacturer Part Number: CDB5461AU
• Description: Eval Bd Sngl Phase Power/Energy
• Manufacturer: Cirrus Logic Inc

Specifications of CDB5461AU

• Main Purpose: Power Management, Energy/Power Meter
• Embedded: Yes, MCU, 8-Bit
• Utilized Ic / Part: CS5461A
• Primary Attributes: 1-Phase, Energy-to-Frequency Output
• Secondary Attributes: GUI, USB, SPI, Microwire Interfaces
• Processor To Be Evaluated: CS5461A, C8051F320
• Interface Type: USB
• Operating Supply Voltage: 5 V
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant, Contains lead / RoHS non-compliant
• Other names: 598-1552

dal inputs so there are no problems with slow edge
times.
The CS5461A can be driven by an external oscillator
ranging from 2.5 to 20 MHz, but the K divider value must
be set such that the internal MCLK will run somewhere
between 2.5 MHz and 5 MHz. The K divider value is set
with the K[3:0] bits in the Configuration Register. As an
example, if XIN = MCLK = 15 MHz, and K is set to 5,
then DCLK is 3 MHz, which is a valid value for DCLK.
5.12 Event Handler
The INT pin is used to indicate that an internal error or
event has taken place in the CS5461A. Writing a logic 1
to any bit in the Mask Register allows the corresponding
bit in the Status Register to activate the INT pin. The in-
terrupt condition is cleared by writing a logic 1 to the bit
that has been set in the Status Register.
The behavior of the INT pin is controlled by the IMODE
and IINV bits of the Configuration Register.
DS661F2
IMODE
0
0
1
Table 3. Interrupt Configuration
IINV
0
1
0
Active-high Level
Active-low Level
Low Pulse
INT Pin
If the interrupt output signal format is set for either falling
or rising edge, the duration of the INT pulse will be at
least one DCLK cycle (DCLK = MCLK/K).
5.12.1 Typical Interrupt Handler
The steps below show how interrupts can be handled.
IMODE
1) All Status bits are cleared by writing 0xFFFFFF to
2) The condition bits which will be used to generate
3) Enable interrupts.
4) Read the Status Register.
5) Disable all interrupts.
6) Branch to the proper interrupt service routine.
7) Clear the Status Register by writing back the read
8) Re-enable interrupts.
9) Return from interrupt service routine.
INITIALIZATION:
INTERRUPT HANDLER ROUTINE:
1
the Status Register.
interrupts are then set to logic 1 in the Mask Reg-
ister.
value in step 4.
Table 3. Interrupt Configuration
IINV
1
High Pulse
INT Pin
CS5461A
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