CDB5461AU Cirrus Logic Inc, CDB5461AU Datasheet - Page 27

• Manufacturer Part Number: CDB5461AU
• Description: Eval Bd Sngl Phase Power/Energy
• Manufacturer: Cirrus Logic Inc

Specifications of CDB5461AU

• Main Purpose: Power Management, Energy/Power Meter
• Embedded: Yes, MCU, 8-Bit
• Utilized Ic / Part: CS5461A
• Primary Attributes: 1-Phase, Energy-to-Frequency Output
• Secondary Attributes: GUI, USB, SPI, Microwire Interfaces
• Processor To Be Evaluated: CS5461A, C8051F320
• Interface Type: USB
• Operating Supply Voltage: 5 V
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant, Contains lead / RoHS non-compliant
• Other names: 598-1552

6.2 Current and Voltage DC Offset Register ( I
6.3 Current and Voltage Gain Register ( I
6.4 Cycle Count Register
DS661F2
MSB
MSB
MSB
-(2
2
2
23
1
Address: 1 (Current DC Offset); 3 (Voltage DC Offset)
0
Default = 0x000000
The DC Offset registers (I
register is updated with the DC offset measured over a computation cycle. DRDY will be asserted at the end of
the calibration. This register may be read and stored for future system offset compensation. The value is repre-
sented in two's complement notation and in the range of -1.0 ≤ I
right of the MSB.
Address: 2 (Current Gain); 4 (Voltage Gain)
Default = 0x400000 = 1.000
The gain registers (I
the register is updated with the gain measured over a computation cycle. DRDY will be asserted at the end of
the calibration. This register may be read and stored for future system gain compensation. The value is in the
range 0.0 ≤ I
iCPU
K[3:0]
Address: 5
Default = 0x000FA0 = 4000
Cycle Count, denoted as N, determines the length of one computation cycle. During continuous conversions,
the computation cycle frequency is (MCLK/K)/(1024∗N). A one second computational cycle period occurs when
MCLK = 4.096 MHz, K = 1, and N = 4000.
)
2
2
2
22
-1
0
2
2
2
gn
21
-2
-1
,V
are sampled, the logic driven by CPUCLK should not be active during the sample edge.
0 = Normal operation (default)
1 = Minimize noise when CPUCLK is driving rising-edge logic
clock DCLK. The internal clock frequency is DCLK = MCLK/K. The value of K can range be-
tween 1 and 16. A value of “0000” will set K to 16 (not zero). K = 1 at reset.
Inverts the CPUCLK clock. In order to reduce the level of noise present when analog signals
Clock divider. A 4-bit binary number used to divide the value of MCLK to generate the internal
gn
< 3.9999, with the binary point to the right of the second MSB.
2
2
2
gn
20
-3
-2
,V
gn
DCoff
)
2
2
2
are initialized to 1.0 on reset. When either a AC or DC Gain calibration is performed,
19
-4
-3
,V
DCoff
2
2
2
18
-5
-4
)
are initialized to 0.0 on reset. When DC Offset calibration is performed, the
2
2
2
17
-6
-5
gn
,V
2
2
2
16
-7
-6
gn
DCoff
)
.....
.....
.....
,V
DCoff
2
2
2
-17
-16
DCoff
6
)
, V
2
2
2
-18
-17
DCoff
5
< 1.0, with the binary point to the
2
2
2
-19
-18
4
2
2
2
-20
-19
3
2
2
2
-21
-20
2
CS5461A
2
2
2
-22
-21
1
LSB
LSB
LSB
2
2
2
-23
-22
0
27