CDB5461AU Cirrus Logic Inc, CDB5461AU Datasheet - Page 30

• Manufacturer Part Number: CDB5461AU
• Description: Eval Bd Sngl Phase Power/Energy
• Manufacturer: Cirrus Logic Inc

Specifications of CDB5461AU

• Main Purpose: Power Management, Energy/Power Meter
• Embedded: Yes, MCU, 8-Bit
• Utilized Ic / Part: CS5461A
• Primary Attributes: 1-Phase, Energy-to-Frequency Output
• Secondary Attributes: GUI, USB, SPI, Microwire Interfaces
• Processor To Be Evaluated: CS5461A, C8051F320
• Interface Type: USB
• Operating Supply Voltage: 5 V
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant, Contains lead / RoHS non-compliant
• Other names: 598-1552

6.11 Current and Voltage AC Offset Register ( V
6.12 PulseRateE
6.13 Temperature Register ( T )
6.14 System Gain Register ( SYS
30
MSB
MSB
MSB
MSB
-(2
-(2
-(2
2
18
0
7
1
Address: 16 (Current AC Offset); 17 (Voltage AC Offset)
Default = 0x000000
The AC Offset Registers (V
AC Offset Calibration updates these registers. This sequence lasts approximately (6N + 30) ADC cycles (where
N is the value of the Cycle Count Register). DRDY will be asserted at the end of the calibration. These values
may be read and stored for future system AC offset compensation. The value is represented in two's comple-
ment notation and in the range of -1.0 ≤ V
ulator due to temperature can be fine adjusted by changing the system gain. The value is represented in two's
complement notation and in the range of -2.0 < SYS
MSB.
Address: 18
Default = 0xFA0000 = 32000.00 Hz
PulseRateE
mental steps. A pulse rate higher than (MCLK/K)/8 will result in a pulse rate setting of (MCLK/K)/8. The value
is represented in unsigned notation, with the binary point to the right of bit #5.
Address: 19
T contains measurements from the on-chip temperature sensor. Measurements are performed during continu-
ous conversions, with the default the Celsius scale (
and in the range of -128.0 ≤ T < 128.0, with the binary point to the right of the eighth MSB.
Address: 20
Default = 0x500000 = 1.25
System Gain (SYS
)
)
)
2
2
2
2
17
-1
6
0
3
2
2
2
2
16
-2
-1
sets the frequency of the E3 pulses. The register’s smallest valid frequency is 2
5
3
Register
Gain
2
2
2
2
15
-3
-2
4
) determines the one’s density of the channel measurements. Small changes in the mod-
2
2
2
2
ACoff
14
-4
-3
3
, I
ACoff
2
2
2
2
13
-5
Gain
-4
2
) are initialized to zero on reset, allowing for uncalibrated normal operation.
)
2
2
2
2
ACoff
12
-6
-5
1
, I
ACoff
2
2
2
2
11
-7
-6
0
< 1.0, with the binary point to the right of the MSB.
o
Gain
C). The value is represented in two's complement notation
ACoff
.....
.....
.....
.....
< 2.0, with the binary point to the right of the second
, I
ACoff
2
2
2
2
-17
-10
-16
1
)
2
2
2
2
-18
-11
-17
0
2
2
2
2
-19
-12
-18
-1
2
2
2
2
-20
-13
-19
-2
2
2
2
2
-21
-14
-20
-3
-4
CS5461A
with 2
2
2
2
2
-22
-15
-21
-4
DS661F2
-5
incre-
LSB
LSB
LSB
LSB
2
2
2
2
-23
-16
-22
-5