CDB5461AU Cirrus Logic Inc, CDB5461AU Datasheet - Page 8

• Manufacturer Part Number: CDB5461AU
• Description: Eval Bd Sngl Phase Power/Energy
• Manufacturer: Cirrus Logic Inc

Specifications of CDB5461AU

• Main Purpose: Power Management, Energy/Power Meter
• Embedded: Yes, MCU, 8-Bit
• Utilized Ic / Part: CS5461A
• Primary Attributes: 1-Phase, Energy-to-Frequency Output
• Secondary Attributes: GUI, USB, SPI, Microwire Interfaces
• Processor To Be Evaluated: CS5461A, C8051F320
• Interface Type: USB
• Operating Supply Voltage: 5 V
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant, Contains lead / RoHS non-compliant
• Other names: 598-1552

8
ANALOG CHARACTERISTICS
VOLTAGE REFERENCE
Notes:
Temperature Channel
Temperature Accuracy
Power Supplies
Power Supply Currents (Active State)
Power Consumption
(Note 3)
Power Supply Rejection Ratio
(Note 4)
PFMON Low-voltage Trigger Threshold
PFMON High-voltage Power-On Trip Point
Reference Output
Output Voltage
Temperature Coefficient
Load Regulation
Reference Input
Input Voltage Range
Input Capacitance
Input CVF Current
1. Applies when the HPF option is enabled.
2. Applies before system calibration.
3. All outputs unloaded. All inputs CMOS level.
4. Measurement method for PSRR: VREFIN tied to VREFOUT, VA+ = VD+ = 5 V, a 150 mV (zero-to-peak) (60 Hz)
5. When voltage level on PFMON is sagging, and LSD bit is at 0, the voltage at which LSD bit is set to 1.
6. If the LSD bit has been set to 1 (because PFMON voltage fell below PMLO), this is the voltage level on PFMON at
7. The voltage at VREFOUT is measured across the temperature range. From these measurements the following
8. Specified at maximum recommended output of 1 µA, source or sink.
sinewave is imposed onto the +5 V DC supply voltage at VA+ and VD+ pins. The “+” and “-” input pins of both input
channels are shorted to AGND. Then the CS5461A is commanded to continuous conversion acquisition mode, and
digital output data is collected for the channel under test. The (zero-to-peak) value of the digital sinusoidal output
signal is determined, and this value is converted into the (zero-to-peak) value of the sinusoidal voltage (measured
in mV) that would need to be applied at the channel’s inputs, in order to cause the same digital sinusoidal output.
This voltage is then defined as Veq. PSRR is then (in dB)
which the LSD bit can be permanently reset back to 0.
formula is used to calculate the VREFOUT Temperature Coefficient:.
Active State (VA+ = 5 V, VD+ = 3.3 V)
Parameter
T C
Parameter
Active State (VA+ = VD+ = 5 V)
V R E F
I
D+
=
(VA+ = 5 V, VD+ = 3.3 V)
(
( V R E F O U T
I
D+
(DC, 50 and 60 Hz)
(VA+ = VD+ = 5 V)
Voltage Channel
Current Channel
V R E F O U T
(Continued)
Stand-By State
M A X
Sleep State
PSRR
- V R E F O U T
(Note 5)
(Note 6)
A V G
(Note 7)
(Note 8)
=
I
A+
20
⋅
M IN
log
Symbol
PSCD
PSCD
PSRR
PMLO
PSCA
)
PMHI
⎧
⎨
⎩
VREFOUT
(
PC
150
--------- -
VREFIN
(
T
V
Symbol
TC
:
T
eq
∆V
A
M A X
VREF
⎫
⎬
⎭
R
- T
1
A
M I N
Min
2.3
45
70
-
-
-
-
-
-
-
-
-
(
+2.4
+2.4
Min
(
-
-
-
-
1 . 0 x 1 0
2.45
2.55
Typ
1.1
2.9
1.7
±5
21
12
10
65
75
6
8
+2.5
+2.5
Typ
25
25
(
6
4
Max
+2.6
+2.6
Max
16.5
2.7
CS5461A
60
10
28
-
-
-
-
-
-
-
-
-
-
-
DS661F2
ppm/°C
Unit
mW
mW
mW
Unit
µW
mA
mA
mA
mV
dB
dB
°C
pF
nA
V
V
V
V