PN5120A0HN1/C2,151 NXP Semiconductors, PN5120A0HN1/C2,151 Datasheet
PN5120A0HN1/C2,151
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PN5120A0HN1/C2,151 Summary of contents
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PN512 Transmission Module Rev. 3.4 — 8 September 2009 111334 1. Introduction This Product data sheet document describes the functionality of the transceiver IC PN512. It includes functional and electrical specifications. 2. General description The PN512 is a highly integrated ...
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... NXP Semiconductors In Card Operation mode, the PN512 transceiver IC is able to answer to a reader/writer command either according to the FeliCa or ISO/IEC 14443A/MIFARE card interface scheme. The PN512 generates the digital load modulated signals and in addition with an external circuit the answer can be sent back to the reader/writer. A complete card ...
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... NXP Semiconductors 3. Features Highly integrated analog circuitry to demodulate and decode responses Buffered output drivers to connect an antenna with minimum number of external components Integrated RF Level detector Integrated data mode detector ISO/IEC 14443A/MIFARE support ISO/IEC 14443B reader/writer functionality Typical operating distance in Reader/Writer mode for communication to a ...
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... NXP Semiconductors 4. Quick reference data Table 1. Quick reference data Symbol Parameter AV Supply Voltage Pad power supply Pad Power Supply DD I Hard Power-down Current HPD I Soft Power-down Current SPD I Digital Supply Current DVDD I Analog Supply Current AVDD I Analog Supply Current, AVDD,RCVOFF receiver switched off ...
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... NXP Semiconductors 6. Block diagram The Analog interface handles the modulation and demodulation of the analog signals according to the Card Receiving mode, Reader/Writer mode and NFCIP-1 mode communication scheme. The RF level detector detects the presence of an external RF-field delivered by the antenna to the RX pin. ...
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... NXP Semiconductors NWR NRD NCS FIFO Control 64 Byte FIFO Control Register Bank MIFARE Classic Unit Random Number Generator Amplitude Rating Reference Voltage Analog Test MUX and DAC VMID AUX1,2 Fig 2. PN512 Block diagram 111334 Product data sheet ALE PVDD 8 bit Parallel, SPI, UART, I2C Interface Control (incl. Automatic Interface Detection & ...
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... NXP Semiconductors 7. Pinning information 7.1 Pinning Fig 3. Pinning configuration HVQFN32 (SOT617-1) Fig 4. Pinning configuration HVQFN40 (SOT618) 111334 Product data sheet terminal 1 index area A1 1 PVDD 2 DVDD 3 DVSS 4 PN512 5 PVSS 6 NRSTPD SIGIN 7 SIGOUT 8 Transparent top view terminal 1 index area PVDD 5 PN512 DVDD ...
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... NXP Semiconductors 7.2 Pin description Table 3. Pin description HVQFN32 Symbol Pin Type PVDD 2 PWR DVDD 3 PWR DVSS 4 PWR PVSS 5 PWR NRSTPD 6 I SIGIN 7 I SIGOUT 8 O SVDD 9 PWR TVSS 10 PWR TX1 11 O TVDD 12 PWR TX2 13 O TVSS 14 PWR AVDD 15 PWR VMID ...
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... NXP Semiconductors Table 4. Pin description HVQFN40 Symbol Pin Type PVDD 5 PWR DVDD 6 PWR DVSS 7 PWR PVSS 8 PWR NRSTPD 9 I SIGIN 10 I SIGOUT 11 O SVDD 12 PWR TVSS 13 PWR TX1 14 O TVDD 15 PWR TX2 16 O TVSS 17 PWR AVDD 18 PWR VMID 19 PWR AVSS 21 PWR ...
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... NXP Semiconductors 8. PN512 register SET 8.1 PN512 registers overview Table 5. Addr Register Name (hex) Page 0: Command and Status 0 PageReg 1 CommandReg 2 ComlEnReg 3 DivlEnReg 4 ComIrqReg 5 DivIrqReg 6 ErrorReg 7 Status1Reg 8 Status2Reg 9 FIFODataReg A FIFOLevelReg B WaterLevelReg C ControlReg D BitFramingReg E CollReg F RFU Page 1: Command 0 PageReg 1 ModeReg 2 TxModeReg 3 RxModeReg 4 TxControlReg ...
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... NXP Semiconductors Table 5. Addr Register Name (hex) 0 PageReg 1 CRCResultReg 2 3 GsNOffReg 4 ModWidthReg 5 TxBitPhaseReg 6 RFCfgReg 7 GsNOnReg 8 CWGsPReg 9 ModGsPReg A TModeReg TPrescalerReg B C TReloadReg D E TCounterValReg Shows the 16-bit actual timer value F Page 3: TestRegister 0 PageReg 1 TestSel1Reg 2 TestSel2Reg 3 TestPinEnReg 4 TestPin ValueReg 5 TestBusReg 6 AutoTestReg 7 VersionReg 8 AnalogTestReg ...
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... NXP Semiconductors 8.1.1 Register bit behavior Depending on the functionality of a register, the access conditions to the register can vary. In principle bits with same behavior are grouped in common registers. In access conditions are described. Table 6. Abbreviation Behavior r RFU RFT 111334 Product data sheet Behavior of register bits and its designation Description read and write These bits can be written and read by the μ ...
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... NXP Semiconductors 8.2 Register description 8.2.1 Page 0: Command and status 8.2.1.1 PageReg Selects the register page. Table 7. Access Rights Table 8. Bit Symbol 7 UsePageSelect PageSelect 8.2.1.2 CommandReg Starts and stops command execution. Table 9. Access Rights Table 10. Bit 111334 Product data sheet PageReg register (address 00h); reset value: 00h, 0000000b ...
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... NXP Semiconductors 8.2.1.3 CommIEnReg Control bits to enable and disable the passing of interrupt requests. Table 11. Access Rights Table 12. Bit Symbol 7 IRqInv 6 TxIEn 5 RxIEn 4 IdleIEn 3 HiAlertIEn 2 LoAlertIEn Allows the low alert interrupt request (indicated by bit LoAlertIRq ErrIEn 0 TimerIEn 111334 Product data sheet CommIEnReg register (address 02h); reset value: 80h, 10000000b ...
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... NXP Semiconductors 8.2.1.4 DivIEnReg Control bits to enable and disable the passing of interrupt requests. Table 13. IRQPushPull Access Rights Table 14. Bit 111334 Product data sheet DivIEnReg register (address 03h); reset value: 00h, 00000000b SiginActIEn ModeIEn CRCIEn RFOnIEn RFOffIEn r/w RFU RFU r/w Description of DivIEnReg bits ...
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... NXP Semiconductors 8.2.1.5 CommIRqReg Contains Interrupt Request bits. Table 15. Access Rights Table 16. All bits in the register CommIRqReg shall be cleared by software. Bit Symbol 7 Set1 6 TxIRq 5 RxIRq 4 IdleIRq 3 HiAlertIRq 2 LoAlertIRq Set to logic 1, when bit LoAlert in register Status1Reg is set. In opposition to 1 ErrIRq 0 TimerIRq 111334 Product data sheet CommIRqReg register (address 04h) ...
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... NXP Semiconductors 8.2.1.6 DivIRqReg Contains Interrupt Request bits Table 17. Access Rights Table 18. All bits in the register DivIRqReg shall be cleared by software. Bit 111334 Product data sheet DivIRqReg register (address 05h); reset value: XXh, 000X00XXb Set2 0 0 SiginActIRq ModeIRq w RFU RFU dy Description of DivIRqReg bits ...
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... NXP Semiconductors 8.2.1.7 ErrorReg Error bit register showing the error status of the last command executed. Table 19. Access Rights Table 20. Bit [1] Command execution will clear all error bits except for bit TempErr. A setting by software is impossible. 111334 Product data sheet ErrorReg register (address 06h); reset value: 00h, 00000000b ...
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... NXP Semiconductors 8.2.1.8 Status1Reg Contains status bits of the CRC, Interrupt and FIFO-buffer. Table 21. Access Rights Table 22. Bit 111334 Product data sheet Status1Reg register (address 07h); reset value: XXh, X100X01Xb RFFreqOK CRCOk CRCReady Description of Status1Reg bits Symbol Description RFFreqOK Indicates if the frequency detected at the RX pin is in the range of 13 ...
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... NXP Semiconductors 8.2.1.9 Status2Reg Contains status bits of the Receiver, Transmitter and Data mode detector. Table 23. TempSensClear I Access Rights Table 24. Bit Symbol 7 TempSensClear TargetActivated 3 MFCrypto1On Modem State 111334 Product data sheet Status2Reg register (address 08h); reset value: 00h, 00000000b CForceHS 0 r/w r/w ...
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... NXP Semiconductors 8.2.1.10 FIFODataReg In- and output of 64 byte FIFO-buffer. Table 25. Access Rights Table 26. Bit 8.2.1.11 FIFOLevelReg Indicates the number of bytes stored in the FIFO. Table 27. Access Rights Table 28. Bit 111334 Product data sheet FIFODataReg register (address 09h); reset value: XXh, XXXXXXXXb Description of FIFODataReg bits ...
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... NXP Semiconductors 8.2.1.12 WaterLevelReg Defines the level for FIFO under- and overflow warning. Table 29. Access Rights Table 30. Bit 8.2.1.13 ControlReg Miscellaneous control bits. Table 31. Access Rights Table 32. Bit Symbol 7 TStopNow 6 TStartNow 5 WrNFCIDtoFIFO 4 Initiator RxLastBits 111334 Product data sheet WaterLevelReg register (address 0Bh); reset value: 08h, 00001000b ...
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... NXP Semiconductors 8.2.1.14 BitFramingReg Adjustments for bit oriented frames. Table 33. Access Rights Table 34. Bit 111334 Product data sheet BitFramingReg register (address 0Dh); reset value: 00h, 00000000b StartSend RxAlign w r/w r/w Description of BitFramingReg bits Symbol Description StartSend Set to logic 1, the transmission of data starts. ...
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... NXP Semiconductors 8.2.1.15 CollReg Defines the first bit collision detected on the RF interface. Table 35. Access Rights Table 36. Bit Symbol 7 ValuesAfterColl CollPosNotValid CollPos 111334 Product data sheet CollReg register (address 0Eh); reset value: XXh, 101XXXXXb Values 0 CollPos AfterColl NotValid r/w RFU r Description of CollReg bits ...
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... NXP Semiconductors 8.2.2 Page 1: Communication 8.2.2.1 PageReg Selects the register page. Table 37. Access Rights Table 38. Bit Symbol 7 UsePage Select Set to logic 1, the value of PageSelect is used as register address PageSelect 111334 Product data sheet PageReg register (address 10h); reset value: 00h, 00000000b UsePage Select ...
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... NXP Semiconductors 8.2.2.2 ModeReg Defines general mode settings for transmitting and receiving. Table 39. Access Rights Table 40. Bit 111334 Product data sheet ModeReg register (address 11h); reset value: 3Bh, 00111011b MSBFirst Detect Sync TxWaitRF RxWaitRF PolSigin ModeDetOff r/w r/w r/w Description of ModeReg bits ...
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... NXP Semiconductors 8.2.2.3 TxModeReg Defines the data rate and framing during transmission. Table 41. Access Rights Table 42. Bit Symbol 7 TxCRCEn TxSpeed 3 InvMod 2 TxMix TxFraming 111334 Product data sheet TxModeReg register (address 12h); reset value: 00h, 00000000b TxCRCEn TxSpeed r Description of TxModeReg bits Description Set to logic 1, this bit enables the CRC generation during data transmission ...
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... NXP Semiconductors 8.2.2.4 RxModeReg Defines the data rate and framing during reception. Table 43. Access Rights Table 44. Bit 111334 Product data sheet RxModeReg register (address 13h); reset value: 00h, 00000000b RxCRCEn RxSpeed r Description of RxModeReg bits Symbol Description RxCRCEn Set to logic 1, this bit enables the CRC calculation during reception. ...
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... NXP Semiconductors 8.2.2.5 TxControlReg Controls the logical behavior of the antenna driver pins Tx1 and Tx2. Table 45. Access Rights Table 46. Bit 111334 Product data sheet TxControlReg register (address 14h); reset value: 80h, 10000000b InvTx2RF InvTx1RF InvTx2RF InvTx1RF On On Off r/w r/w r/w ...
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... NXP Semiconductors 8.2.2.6 TxAutoReg Controls the settings of the antenna driver. Table 47. Access Rights Table 48. Bit 111334 Product data sheet TxAutoReg register (address 15h); reset value: 00h, 00000000b AutoRF Force100 Auto 0 OFF ASK WakeUp r/w r/w r/w RFU Description of TxAutoReg bits Symbol ...
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... NXP Semiconductors 8.2.2.7 TxSelReg Selects the sources for the analog part. Table 49. Access Rights Table 50. Bit Symbol DriverSel 111334 Product data sheet TxSelReg register (address 16h); reset value: 10h, 00010000b DriverSel RFU RFU r/w r/w Description of TxSelReg bits Description Reserved for future use. ...
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... NXP Semiconductors Table 50. Bit Symbol SigOutSel 111334 Product data sheet Description of TxSelReg bits …continued Description Selects the input for the SIGOUT Pin. Value Description 0000 Tristate 0001 Low 0010 High 0011 TestBus signal as defined by bit TestBusBitSel in register TestSel1Reg. 0100 Modulation signal (envelope) from the internal coder ...
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... NXP Semiconductors 8.2.2.8 RxSelReg Selects internal receiver settings. Table 51. Access Rights Table 52. Bit 8.2.2.9 RxThresholdReg Selects thresholds for the bit decoder. Table 53. Access Rights Table 54. Bit 111334 Product data sheet RxSelReg register (address 17h); reset value: 84h, 10000100b UartSel r/w r/w ...
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... NXP Semiconductors 8.2.2.10 DemodReg Defines demodulator settings. Table 55. Access Rights Table 56. Bit Symbol AddIQ 4 FixIQ TauRcv TauSync 111334 Product data sheet DemodReg register (address 19h); reset value: 4Dh, 01001101b AddIQ FixIQ r/w r/w r/w RFU Description of DemodReg bits Description Defines the use of I and Q channel during reception Note: FixIQ has to be set to logic 0 to enable the following settings ...
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... NXP Semiconductors 8.2.2.11 FelNFC1Reg Defines the length of the FeliCa Sync bytes and the minimum length of the received packet. Table 57. Access Rights Table 58. Bit Symbol FelSyncLen Defines the length of the Sync bytes DataLenMin These bits define the minimum length of the accepted packet length: ...
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... NXP Semiconductors 8.2.2.12 FelNFC2Reg Defines the maximum length of the received packet. Table 59. Access Rights Table 60. Bit 111334 Product data sheet FelNFC2Reg register (address1Bh); reset value: 00h, 00000000b 7 6 WaitForSelected ShortTimeSlot r/w r/w Description of FelNFC2Reg bits Symbol Description WaitForSelected Set to logic 1, the AutoColl command is only terminated automatically when: 1 ...
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... NXP Semiconductors 8.2.2.13 MifNFCReg Defines ISO/IEC 14443A/MIFARE/NFC specific settings in target or Card Operating mode. Table 61. Access Rights Table 62. Bit 111334 Product data sheet MifNFCReg register (address 1Ch); reset value: 62h, 01100010b SensMiller r/w r/w r/w r/w Description of MifNFCReg bits Symbol Description SensMiller These bits define the sensitivity of the Miller decoder ...
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... NXP Semiconductors 8.2.2.14 ManualRCVReg Allows manual fine tuning of the internal receiver. Remark: For standard applications it is not recommended to change this register settings. Table 63. Access Rights Table 64. Bit 111334 Product data sheet ManualRCVReg register (address 1Dh); reset value: 00h, 00000000b FastFilt Delay ...
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... NXP Semiconductors 8.2.2.15 TypeBReg Table 65. Access Rights Table 66. Bit 8.2.2.16 SerialSpeedReg Selects the speed of the serial UART interface. Table 67. Access Rights Table 68. Bit 111334 Product data sheet TypeBReg register (address 1Eh); reset value: 00h, 00000000b RxSOF RxEOF 0 EOFSO Req Req FWidth ...
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... NXP Semiconductors 8.2.3 Page 2: Configuration 8.2.3.1 PageReg Selects the register page. Table 69. Access Rights Table 70. Bit 8.2.3.2 CRCResultReg Shows the actual MSB and LSB values of the CRC calculation. Note: The CRC is split into two 8-bit register. Note: Setting the bit MSBFirst in ModeReg register reverses the bit order, the byte order is not changed ...
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... NXP Semiconductors 8.2.3.3 GsNOffReg Selects the conductance for the N-driver of the antenna driver pins TX1 and TX2 when the driver is switched off. Table 75. Access Rights Table 76. Bit 111334 Product data sheet GsNOffReg register (address 23h); reset value: 88h, 10001000b CWGsNOff r/w ...
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... NXP Semiconductors 8.2.3.4 ModWidthReg Controls the modulation width settings. Table 77. Access Rights Table 78. Bit 8.2.3.5 TxBitPhaseReg Adjust the bitphase at 106 kbit during transmission. Table 79. Access Rights Table 80. Bit 111334 Product data sheet ModWidthReg register (address 24h); reset value: 26h, 00100110b r/w ...
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... NXP Semiconductors 8.2.3.6 RFCfgReg Configures the receiver gain and RF level detector sensitivity. Table 81. Access Rights Table 82. Bit 111334 Product data sheet RFCfgReg register (address 26h); reset value: 48h, 01001000b RFLevelAmp RxGain r/w r/w r/w Description of RFCfgReg bits Symbol Description RFLevelAmp Set to logic 1, this bit activates the RF level detectors’ amplifier. ...
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... NXP Semiconductors 8.2.3.7 GsNOnReg Selects the conductance for the N-driver of the antenna driver pins TX1 and TX2 when the driver is switched on. Table 83. Access Rights Table 84. Bit 8.2.3.8 CWGsPReg Defines the conductance of the P-driver during times of no modulation Table 85. Access Rights Table 86. ...
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... NXP Semiconductors 8.2.3.9 ModGsPReg Defines the driver P-output conductance during modulation. Table 87. Access Rights Table 88. Bit [1] If Force100ASK is set to logic 1, the value of ModGsP has no effect. 8.2.3.10 TMode Register, TPrescaler Register Defines settings for the timer. Note: The Prescaler value is split into two 8-bit registers Table 89 ...
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... NXP Semiconductors Table 90. Bit Symbol TGated 4 TAutoRestart TPrescaler_Hi Defines higher 4 bits for TPrescaler. Table 91. Access Rights Table 92. Bit 111334 Product data sheet Description of TModeReg bits …continued Description The internal timer is running in gated mode. Note: In the gated mode, the bit TRunning is 1 when the timer is enabled by the register bits ...
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... NXP Semiconductors 8.2.3.11 TReloadReg Describes the 16-bit long timer reload value. Note: The Reload value is split into two 8-bit registers. Table 93. Access Rights Table 94. Bit Table 95. Access Rights Table 96. Bit 111334 Product data sheet TReloadReg (Higher bits) register (address 2Ch); reset value: 00h, 00000000b ...
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... NXP Semiconductors 8.2.3.12 TCounterValReg Contains the current value of the timer. Note: The Counter value is split into two 8-bit register. Table 97. Access Rights Table 98. Bit Table 99. Access Rights Table 100. Description of lower TCounterValReg bits Bit 8.2.4 Page 3: Test 8.2.4.1 PageReg Selects the register page. ...
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... NXP Semiconductors Table 102. Description of PageReg bits Bit 111334 Product data sheet Symbol Description UsePageSelect Set to logic 1, the value of PageSelect is used as register address A5 and A4. The LSB-bits of the register address are defined by the address pins or the internal address latch, respectively. Set to logic 0, the whole content of the internal address latch defines the register address. The address pins are used as described in Section 10.1 “ ...
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... NXP Semiconductors 8.2.4.2 TestSel1Reg General test signal configuration. Table 103. TestSel1Reg register (address 31h); reset value: 00h, 00000000b Access Rights Table 104. Description of TestSel1Reg bits Bit 8.2.4.3 TestSel2Reg General test signal configuration and PRBS control Table 105. TestSel2Reg register (address 32h); reset value: 00h, 00000000b ...
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... NXP Semiconductors 8.2.4.4 TestPinEnReg Enables the pin output driver on the 8-bit parallel bus. Table 107. TestPinEnReg register (address 33h); reset value: 80h, 10000000b Access Rights Table 108. Description of TestPinEnReg bits Bit 8.2.4.5 TestPinValueReg Defines the values for the 7-bit parallel port when it is used as I/O. ...
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... NXP Semiconductors 8.2.4.6 TestBusReg Shows the status of the internal testbus. Table 111. TestBusReg register (address 35h); reset value: XXh, XXXXXXXXb Access Rights Table 112. Description of TestBusReg bits Bit 8.2.4.7 AutoTestReg Controls the digital selftest. Table 113. AutoTestReg register (address 36h); reset value: 40h, 01000000b Access Rights Table 114 ...
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... NXP Semiconductors 8.2.4.9 AnalogTestReg Controls the pins AUX1 and AUX2 Table 117. AnalogTestReg register (address 38h); reset value: 00h, 00000000b 7 AnalogSelAux1 Access Rights r/w r/w Table 118. Description of AnalogTestReg bits Bit Symbol Description AnalogSelAux1 Controls the AUX pin AnalogSelAux2 Note: All test signals are described in ...
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... NXP Semiconductors 8.2.4.10 TestDAC1Reg Defines the testvalues for TestDAC1. Table 119. TestDAC1Reg register (address 39h); reset value: XXh, 00XXXXXXb Access Rights Table 120. Description of TestDAC1Reg bits Bit 8.2.4.11 TestDAC2Reg Defines the testvalue for TestDAC2. Table 121. TestDAC2Reg register (address 3Ah); reset value: XXh, 00XXXXXXb ...
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... NXP Semiconductors 8.2.4.13 RFTReg Table 125. RFTReg register (address 3Ch); reset value: FFh, 11111111b Access Rights Table 126. Description of RFTReg bits Bit Table 127. RFTReg register (address 3Dh, 3Fh); reset value: 00h, 00000000b Access Rights Table 128. Description of RFTReg bits Bit Table 129. RFTReg register (address 3Eh) ...
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... NXP Semiconductors 9. Operating modes PN512 transceiver IC supports the following operating modes: • Reader/Writer mode supporting ISO/IEC 14443A/MIFARE and FeliCa scheme • Card Operation mode supporting ISO/IEC 14443A/MIFARE and FeliCa scheme • NFCIP-1 mode The modes support different transfer speeds and modulation schemes. The following chapters will explain the different modes in detail ...
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... NXP Semiconductors Table 131. Communication overview for ISO/IEC 14443A/MIFARE reader/writer Communication direction PN512 → PICC (send data from the PN512 to a card) PICC → PN512 (receive data from a card) The contactless UART of PN512 and a dedicated external host controller are required to handle the complete MIFARE/ISO/IEC 14443A/MIFARE protocol. ...
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... NXP Semiconductors 9.1.2 FeliCa reader/writer functionality The FeliCa mode is the general reader/writer to card communication scheme according to the FeliCa specification. The following diagram describes the communication on a physical level, the communication overview describes the physical parameters. FeliCa Reader PN512 Fig 8. FeliCa reader/writer communication diagram Table 132 ...
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... The following registers and bits cover the ISO/IEC 14443B communication scheme reference documentation the international standard ISO/IEC 14443 'Identification cards- Contactless integrated circuit(s) cards- Proximity cards, part 1-4' can be taken. Note: NXP Semiconductors does not offer a software library to design in the ISO/IEC 14443B protocol. 9.2 NFCIP-1 mode The NFCIP-1 communication differentiates between an active and a Passive Communication mode ...
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... NXP Semiconductors 9.2.1 Active communication mode Active communication mode means both the initiator and the target are using their own RF field to transmit data. Host NFC Initiator powered to generate RF field Host NFC Initiator powered for digital processing Fig 10. Active communication mode Table 135. Communication overview for Active communication mode ...
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... NXP Semiconductors 9.2.2 Passive communication mode Passive Communication mode means that the target answers to an initiator command in a load modulation scheme. The initiator is active meaning generating the RF field. Fig 11. Passive communication mode Table 136. Communication overview for Passive communication mode Communication direction Initiator → ...
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... NXP Semiconductors 9.2.3 NFCIP-1 framing and coding The NFCIP-1 framing and coding in Active and Passive Communication mode is defined in the NFCIP-1 standard. Table 137. Framing and coding overview Transfer speed 106 kbit/s 212 kbit/s 424 kbit/s 9.2.4 NFCIP-1 protocol support The NFCIP-1 protocol is not completely described in this document. For detailed explanation of the protocol refer to the NFCIP-1 standard ...
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... NXP Semiconductors 9.3.1 MIFARE Card operation mode Table 138. MIFARE Card operation mode Communication direction reader / writer → PN512 PN512 → reader/ writer 9.3.2 FeliCa Card operation mode FeliCa Card operation mode Communication direction reader/writer → PN512 PN512 → reader/ writer ...
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... NXP Semiconductors 10. Digital interfaces 10.1 Automatic host controller interface type detection The PN512 supports direct interfacing of various host controllers as the 8-bit parallel, SPI and serial UART interface type. The PN512 resets its interface and checks the current host controller interface type automatically having performed a Power-On or Hard Reset. ...
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... NXP Semiconductors 10.2.1 General An interface compatible to an SPI interface enables a high-speed serial communication between the PN512 and a μ-Controller Mbit in order to handle the requirements for the NFCIP-1 communication. The implemented SPI compatible interface is according to a standard SPI interface. For timing specification refer to Fig 13 ...
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... NXP Semiconductors Write data: To write data to the PN512 using the SPI interface the following byte order has to be used possible to write out up to n-data bytes by only sending one’s address byte. The first send byte defines both, the mode itself and the address byte. ...
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... NXP Semiconductors 10.3.2 Selection of the transfer speeds The internal UART interface is compatible to an RS232 serial interface. Table 144 “Selectable transfer speeds” and relevant register settings. The resulting transfer speed error is less than 1.5% for all described transfer speeds. The default transfer speed is 9.6 kbit. ...
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... NXP Semiconductors 10.3.3 Framing Table 145. UART Framing For data and address bytes the LSB bit has to be sent first. Note: No parity bit is used during transmission. Read data: To read out data using the UART interface the flow described below has to be used. The first send byte defines both the mode itself and the address ...
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... NXP Semiconductors Table 147. Byte order to write data RX TX Fig 16. Schematic Diagram to Write Data Remark: The data byte can be send directly after the address byte on RX. Address byte: The address byte has to fulfill the following format. The MSB of the first byte sets the used mode ...
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... SCL and SDA is activated. For timing requirements refer to 111334 Product data sheet 2 C) bus interface is supported to enable a low cost, low pin count serial bus 2 C interface is implemented according the NXP Semiconductors I pullup network Configuration wiring C interface Section 24.9 “I Rev. 3.4 — 8 September 2009 ...
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... NXP Semiconductors 10.4.2 Data validity Data on the SDA line shall be stable during the HIGH period of the clock. The HIGH or LOW state of the data line shall only change when the clock signal on SCL is LOW. Fig 18. Bit transfer on the I 10.4.3 START and STOP conditions To handle the data transfer on the I are defined ...
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... NXP Semiconductors 10.4.4 Byte format Each byte has to be followed by an acknowledge bit. Data is transferred with the MSB first, see Figure unrestricted but shall fulfill the read/write cycle format. 10.4.5 Acknowledge An acknowledge at the end of one data byte is mandatory. The acknowledge-related clock pulse is generated by the master ...
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... NXP Semiconductors 10.4.6 7-bit addressing During the I to determine which slave will be selected by the master. During device configuration, the designer has to ensure, that no collision with these reserved addresses is possible. Check the corresponding I list of reserved addresses. For all PN512devices the upper 4 bits of the device bus address are reserved by NXP and set to 0101(bin) ...
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... NXP Semiconductors 10.4.8 Register read access To read out data from a specific register address of the PN512 the host controller shall use the procedure: First a write access to the specific register address has to be performed as indicated in the following frame. The first byte of a frame indicates the device address according to the I second byte indicates the register address ...
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... NXP Semiconductors 10.4.9 HS mode In High-speed mode (HS mode) the device can transfer information at data rates 3.4 Mbit, it remains fully downward compatible with Fast- or Standard mode (F/S mode) for bi-directional communication in a mixed-speed bus system. 10.4.10 High speed transfer To achieve a data rates 3.4 Mbit the following improvements have been made to the regular I • ...
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... NXP Semiconductors 2 Fig 25 mode protocol frame 10.4.12 Switching from F mode and Vice Versa After reset and initialization, the PN512 is in Fast mode (which is in effect F/S mode as Fast mode is downward compatible to Standard mode). The connected PN512 recognizes the “S 00001XXX A” sequence and switches its internal circuitry from the Fast mode setting to the HS mode setting ...
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... NXP Semiconductors 10.4.13 PN512 at lower speed modes PN512 is fully downwards compatible, and can be connected to an F/S mode I system master code will be transmitted in such a configuration, the device stays in F/S mode and communicates at F/S mode speeds. 10.5 8-bit parallel interface The PN512 supports two different types of 8-bit parallel interfaces, Intel and Motorola compatible modes ...
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... NXP Semiconductors 10.5.3 Common Read/Write strobe Non Multiplexed Address LOW LOW LOW HIGH HIGH LOW Multiplexed Address/Data Adress Strobe (AS) Not Data Strobe (NDS) Read Not Write (RD/NWR) Remark: *depending on the package type. Fig 27. Connection to host controller with common Read/Write strobes For timing requirements refer to ...
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... NXP Semiconductors 11. AnaLog interface and contactless UART 11.1 General The PN512 supports different Contactless Communication modes. The integrated contactless UART supports the external μ-Controller online with framing and error checking of the protocol requirements for the different selected communication schemes as Card Operation mode, Reader/Writer Operating mode or NFIP-1 mode up to 424 kbit. ...
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... NXP Semiconductors Table 150. Settings for TX1 TX1RFEn Force InvTx1 100ASK RFON Table 151. Settings for TX2 TX2RFEn Force TX2CW InvTx2 100ASK RFON 111334 Product data sheet InvTx1 Envelope TX1 RFOFF RF_n 1 RF_n RF_n InvTx2 Enve TX2 RFOFF lope RF_n 1 RF_n ...
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... NXP Semiconductors The following abbreviations are used: • RF: 13.56 MHz clock derived from 27.12 MHz quartz divided by 2 • RF_n: inverted 13.56 MHz clock • gspmos: Conductance, configuration of the PMOS array • gspmos: Conductance, configuration of the NMOS array • pCW: PMOS conductance value for continuous wave defined by CWGsP register • ...
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... NXP Semiconductors To increase the sensitivity of the RF level detector an amplifier can be activated by setting the bit RFLevelAmp in register RFCfgReg to 1. Remark: During soft Power-down mode the RF level detector amplifier is automatically switched off to ensure that the power consumption is less than 10 μ Remark: With typical antennas lower sensitivity levels can provoke misleading results because of intrinsic noise in the environment ...
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... ISO/IEC 14443A signal sent by the secure IC. The SIGOUT pin can provide a digital signal and a clock to communicate to the secure IC. A secure IC can be the smart card IC provided by NXP Semiconductors. The PN512 has an extra supply pin (SVDD and PVSS as Ground line) for the SIGIN and SIGOUT pads ...
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... NXP Semiconductors Fig 30. Communication flows using the S Configured in the Secure Access Mode the host controller can directly communicate to the Secure IC via SIGIN/SIGOUT. In this mode the PN512 generates the RF clock and performs the communication on the SIGOUT line. To enable the Secure Access module mode the clock has to be derived by the internal oscillator of the PN512, see bits SAMClockSel in register TestSel1Reg ...
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... NXP Semiconductors 11.6.1 Signal shape for Felica S The FeliCa secure IC is connected to the PN512 via the pins SIGOUT and SIGIN. The signal at SIGOUT contains the information of the 13.56 MHz clock and the digitized demodulated signal. The clock and the demodulated signal is combined by using the logical function exclusive or ...
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... NXP Semiconductors 11.6.2 Waveform shape for ISO/IEC 14443A and MIFARE S The secure IC, e.g. the SmartMX is connected to the PN512 via the pins SIGOUT and SIGIN. The waveform shape at SIGOUT is a digital 13.56 MHz Miller coded signal with levels between PVSS and PVDD derived out of the external 13.56 MHz carrier signal in case of the Contactless Card mode or internally generated in terms of Secure Access mode ...
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... NXP Semiconductors 11.7 Hardware support for FeliCa and NFC polling 11.7.1 Polling sequence functionality for initiator 1. Timer: The PN512 has a timer, which can be programmed in a way that it generates an interrupt at the end of each timeslot required an interrupt is generated at the end of the last timeslot. ...
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... NXP Semiconductors 11.7.3 Additional hardware support for FeliCa and NFC Additionally to the polling sequence support for the Felica mode, the PN512 supports the check of the Len-byte. The received Len-byte in accordance to the registers FelNFC1Reg and FelNFC2Reg: DataLenMin in register FelNFC1Reg defines the minimum length of the accepted packet length ...
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... NXP Semiconductors 12. FIFO-buffer 12.1 Overview An 64*8-bit FIFO-buffer is implemented in the PN512. It buffers the input and output data stream between the host controller and the internal state machine of the PN512. Thus possible to handle data streams with lengths bytes without taking timing constraints into account. ...
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... NXP Semiconductors 12.4 Status information about the FIFO-buffer The host controller may obtain the following data about the FIFO-buffers status: • Number of bytes already stored in the FIFO-buffer: FIFOLevel in register FIFOLevelReg • Warning, that the FIFO-buffer is almost full: HiAlert in register Status1Reg • ...
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... NXP Semiconductors 13. Timer unit A timer unit is implemented in the PN512. The external host controller may use this timer to manage timing relevant tasks. The timer unit may be used in one of the following configurations: • Time-out counter • Watch-dog counter • Stop watch • Programmable one-shot • ...
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... NXP Semiconductors 14. Interrupt request system 14.1 Overview The PN512 indicates certain events by setting bit IRq in the register Status1Reg and additionally, if activated, by pin IRQ. The signal on pin IRQ may be used to interrupt the host controller using its interrupt handling capabilities. This allows the implementation of efficient host controller software ...
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... NXP Semiconductors Table 153. Interrupt sources Interrupt bit TimerIRq TxIRq CRCIRq RxIRq IdleIRq HiAlertIRq LoAlertIRq RFOnIRq RFOffIRq ErrIRq ModeIRq 111334 Product data sheet Interrupt source Is set automatically, when Timer Unit the timer counts from Transmitter a transmitted data stream ends CRC co-processor ...
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... NXP Semiconductors 15. Oscillator circuitry The clock applied to the PN512 acts as time basis for the coder and decoder of the synchronous system. Therefore stability of the clock frequency is an important factor for proper performance. To obtain highest performance, clock jitter has small as possible. This is best achieved by using the internal oscillator buffer with the recommended circuitry ...
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... NXP Semiconductors 16. Power reduction modes 16.1 Hard Power-down A Hard Power-down is enabled with LOW level on pin NRSTPD. This turns off all internal current sinks as well as the oscillator. All digital input buffers are separated from the input pads and clamped internally (except pin NRSTPD itself). The output pins are frozen at a certain value ...
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... NXP Semiconductors 17. Reset and Oscillator start up time 17.1 Reset timing requirements The reset signal is filtered by a hysteresis circuit and a spike filter (rejects signals shorter than 10 ns) before it enters the digital circuit. In order to perform a reset, the signal has to be low for at least 100 ns. ...
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... NXP Semiconductors 18. PN512 Command set 18.1 General description The PN512 behavior is determined by a state machine capable to perform a certain set of commands. By writing the according command to the Command-Register the command is executed. Arguments and/or data necessary to process a command are exchanged via the FIFO-buffer. 18.2 General behavior • ...
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... NXP Semiconductors 18.3.1 PN512 Command description 18.3.1.1 Idle command The PN512 is in Idle mode. This command is also used to terminate the actual command. 18.3.1.2 Config command To use the automatic MIFARE Anticollision, FeliCa Polling and NFCID3 the data used for these transactions has to be stored internally. All the following data have to be written to the FIFO in this order: • ...
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... NXP Semiconductors 18.3.1.4 CalcCRC command The content of the FIFO is transferred to the CRC co-processor and a CRC calculation is started. The result of this calculation is stored in the CRCResultReg register. The CRC calculation is not limited to a dedicated number of bytes. The calculation is not stopped, when the FIFO gets empty during the data stream. The next byte written to the FIFO is added to the calculation ...
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... NXP Semiconductors 18.3.1.8 Transceive command This circular command repeats transmitting data from the FIFO and receiving data from the RF field continuously. If the bit Initiator in the register ControlReg is set to logic 1, it indicates that the first action is transmitting and after having finished transmission the receiver is activated to receive data ...
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... NXP Semiconductors HALT REQA, WUPA, nAC, REQA, WUPA nSELECT, WUPA, HLTA AC, Error nAC, READY* SELECT, nSELECT, Error SELECT ACTIVE* HLTA Fig 37. Autocoll Command NFCIP-1 106 kbps Passive Communication mode: The MIFARE anticollision is finished and the command has automatically changed to Transceive. The FIFO contains the ATR_REQ frame including the start byte F0h. The bit TargetActivated in the Status2Reg register is set to logic 1 ...
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... NXP Semiconductors FeliCa (Card Operation mode): The FeliCa polling command is finished and the command has automatically changed to transceive. The FIFO contains the first command followed after the Polling by the FeliCa protocol.The bit TargetActivated in the Status2Reg register is set to logic 1. 18.3.1.10 MFAuthent command This command handles the MIFARE authentication in Reader/Writer mode to enable a secure communication to any MIFARE card ...
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... NXP Semiconductors 19. Testsignals 19.1 Selftest The PN512 has the capability to perform a digital selftest. To start the selftest the following procedure has to be performed: 1. Perform a soft reset. 2. Clear the internal buffer by writing 25 bytes of 00h and perform the Config Command. 3. Enable the Selftest by writing the value 09h to the register AutoTestReg. ...
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... NXP Semiconductors Table 157. Testsignal routing (TestSel2Reg = 0Dh) Pins Testsignal Table 158. Description of Testsignals Pins Table 159. Testsignal routing (TestSel2Reg = 19h) Pins Testsignal Table 160. Description of Testsignals Pins 111334 Product data sheet clkstable clk27/8 clk27rf/8 Testsignal Description clkstable shows if the oscillator delivers a stable signal. ...
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... NXP Semiconductors 19.3 Testsignals at pin AUX Table 161. Testsignals description SelAux 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Each signal can be switched to pin AUX1 or AUX2 by setting SelAux1 or SelAux2 in the register AnalogTestReg. Note: The DAC has a current output recommended to use a 1 kΩ pull-down resistance at pins AUX1/AUX2 ...
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... NXP Semiconductors 20. Application design-in information The figure below shows a typical circuit diagram, using a complementary antenna connection to the PN512. The antenna tuning and RF part matching is described in the application note “NFC Transmission Module Antenna and RF Design Guide”. Fig 38. Typical circuit diagram 111334 Product data sheet Rev. 3.4 — ...
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... NXP Semiconductors 21. Limiting values Table 162. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter AV Supply voltage Input voltage in, abs V in, SigIn P Total power dissipation per package tot (V and DV in short cut mode) BUS DD T Junction temperature range J ESD Susceptibility (Human Body model) 1500 Ω ...
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... NXP Semiconductors 24. Characteristics 24.1 Input pin characteristics 24.1.1 Input pin characteristics for pins A0, A1, A2, A3, A4, A5, NCS, NWR, NRD and NRESET Table 165. Input pin characteristics for pins A0, A1, A2, A3, A4, A5, NCS, NWR, NRD, SIGIN and NRESET Symbol Parameter I Input Leakage current ...
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... NXP Semiconductors 24.1.5 Output pin characteristics for pin SIGOUT Table 169. Output pin characteristics for Pin SIGOUT Symbol Parameter V Output voltage HIGH OH V Output voltage LOW OL I Output current drive LOW OL I Output current drive HIGH OH 24.1.6 Output pin characteristics for pin IRQ Table 170 ...
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... NXP Semiconductors 24.1.9 Output pin characteristics for pins AUX1 and AUX2 Table 173. Input/Output pin characteristics for pins AUX1 and AUX2 Symbol Parameter V Output voltage HIGH OH V Output voltage LOW OL I Output current drive LOW OL I Output current drive HIGH OH 24.1.10 Output pin characteristics for pins TX1 and TX2 Table 174 ...
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... NXP Semiconductors 24.2 Current consumption Table 175. Current consumption Symbol Parameter I Hard Power-down Current AV HPD I Soft Power-down Current SPD I Digital Supply Current DVDD I Analog Supply Current AVDD I Analog Supply Current, AVDD,RCVOFF receiver switched off I Pad Supply Current PVDD I Transmitter Supply TVDD ...
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... NXP Semiconductors 24.4 RX input sensitivity Table 177. RX input sensitivity Symbol Parameter m Minimum Modulation index, Miller coded AV RX,Mill V Minimum modulation voltage RXMod,Man [1] The minimum modulation voltage is valid for all modulation schemes except Miller coded signals. Figure 39 “RX input voltage range” Fig 39. RX input voltage range ...
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... NXP Semiconductors 24.5 Clock frequency Table 178. Clock frequency Symbol Parameter f Clock Frequency OSCIN d Duty Cycle of Clock Frequency FEC t Jitter of Clock Edges jitter 24.6 XTAL oscillator Table 179. XTAL oscillator Symbol Parameter V Output Voltage High XTAL2 OH,OSCOUT V Output Voltage Low XTAL2 ...
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... NXP Semiconductors 24.8 Timing for the SPI compatible interface Table 181. Timing specification for SPI Symbol Parameter t NSS high before communication NHNL t SCK low pulse width SCKL t SCK high pulse width SCKH t SCK high to data changes SHDX t data changes to SCK high ...
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... NXP Semiconductors 2 24 timing 2 Table 182. Overview I C timing in fast mode Symbol Parameter f SCL clock frequency SCL t Hold time (repeated) START condition. After this HD;STA period, the first clock pulse is generated t Set-up time for a repeated START condition SU;STA t Set-up time for STOP condition SU ...
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... NXP Semiconductors 24.10 8-bit parallel interface timing 24.10.1 AC symbols Each timing symbol has five characters. The first character is always 't' for time. The other characters indicate the name of a signal or the logic state of that signal (depending on position): Table 183. AC symbols Designation Example ...
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... NXP Semiconductors ALE NCS NWR NRD D0 ... D7 A0 ... A3 Fig 42. Timing diagram for separated Read/Write strobe Remark: For separated address and data bus the signal ALE is not relevant and the multiplexed addresses on the data bus don’t care. For the multiplexed address and data bus the address lines have to be connected as described in chapter Automatic host controller Interface Type Detection ...
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... NXP Semiconductors ALE NCS R/NW NDS D0 ... D7 A0 ... A3 Fig 43. Timing diagram for common Read/Write strobe Remark: For separated address and data bus the signal ALE is not relevant and the multiplexed addresses on the data bus don’t care. For the multiplexed address and data bus the address lines have to be connected as described in Automatic μ ...
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... NXP Semiconductors 25. Package information The PN512 can be delivered in 2 different packages. Table 186. Package information Package HVQFN32 HVQFN40 111334 Product data sheet Remarks 8-bit parallel interface not supported Supports the 8-bit parallel interface Rev. 3.4 — 8 September 2009 PN512 Transmission Module PUBLIC © ...
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... NXP Semiconductors 26. Package outline HVQFN32: plastic, heatsink very thin quad flat package; no leads; 32 terminals; body 0.85 mm terminal 1 index area pin 1 index 1 32 DIMENSIONS (mm are the original dimensions UNIT ( max. max. 0.35 5.05 mm 1.00 0.80 0.18 4.95 Note 1. Plastic or metal protrusions of 0.076 mm maximum per side are not included. ...
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... NXP Semiconductors HVQFN40: plastic, heatsink very thin quad flat package; no leads; 40 terminals; body 0.85 mm terminal 1 index area pin 1 index 1 40 DIMENSIONS (mm are the original dimensions (1) UNIT max. max. 0.35 6.05 4.25 mm 0.80 1.00 0.18 5.95 3.95 Note 1. Plastic or metal protrusions of 0.076 mm maximum per side are not included. ...
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... NXP Semiconductors 27. Abbreviations Table 187. Abbreviations Acronym ASK SOF EOF PCD PICC PCD → PICC PICC → PCD Initiator Modulation Index The modulation index is defined as the voltage ratio (Vmax - Vmin)/ Loadmodulation Index Target 111334 Product data sheet Description Amplitude Shift keying ...
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... NXP Semiconductors 28. Revision history Table 188. Revision history Document ID Release date 111334 8 September 2009 • Modifications: Section 8.2.3.10 on page 45 • Table 90 on page • Table 92 on page 46 • Section 13 on page • Section 19.2 on page 103 111333 21 January 2009 • Modifications: General rewording of MIFARE designation and commercial conditions • ...
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... Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice ...
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... NXP Semiconductors 31. Tables Table 1. Quick reference data . . . . . . . . . . . . . . . . . . . . .4 Table 2. Ordering information . . . . . . . . . . . . . . . . . . . . .4 Table 3. Pin description HVQFN32 . . . . . . . . . . . . . . . . .8 Table 4. Pin description HVQFN40 . . . . . . . . . . . . . . . . .9 Table 5. PN512 registers overview . . . . . . . . . . . . . . . .10 Table 6. Behavior of register bits and its designation . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 Table 7. PageReg register (address 00h); reset value: 00h, 0000000b . . . . . . . . . . . . . . .13 Table 8. Description of PageReg bits . . . . . . . . . . . . . . .13 Table 9. CommandReg register (address 01h) ...
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... NXP Semiconductors Table 66. Description of TypeBReg bits . . . . . . . . . . . . . .39 Table 67. SerialSpeedReg register (address 1Fh); reset value: EBh, 11101011b . . . . . . . . . . . . . .39 Table 68. Description of SerialSpeedReg bits . . . . . . . . .39 Table 69. PageReg register (address 20h); reset value: 00h, 00000000b . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 Table 70. Description of PageReg bits . . . . . . . . . . . . . . .40 Table 71. CRCResultReg register (address 21h); reset value: FFh, 11111111b . . . . . . . . . . . . . . .40 Table 72. Description of CRCResultReg bits . . . . . . . . . .40 Table 73. CRCResultReg register (address 22h) ...
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... NXP Semiconductors Table 132.Communication overview for FeliCa reader/writer . . . . . . . . . . . . . . . . . . . . . . . . . . .58 Table 133.FeliCa framing and coding . . . . . . . . . . . . . . . .58 Table 134.Start value for the CRC Polynomial: (00h), (00h .58 Table 135.Communication overview for Active communication mode . . . . . . . . . . . . . . . . . . . .60 Table 136.Communication overview for Passive communication mode . . . . . . . . . . . . . . . . . . . .61 Table 137.Framing and coding overview .62 Table 138 ...
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... NXP Semiconductors 32. Figures Fig 1. Simplified PN512 Block diagram . . . . . . . . . . . . . .5 Fig 2. PN512 Block diagram . . . . . . . . . . . . . . . . . . . . . .6 Fig 3. Pinning configuration HVQFN32 (SOT617- Fig 4. Pinning configuration HVQFN40 (SOT618 Fig 5. Reader/Writer mode .56 Fig 6. ISO/IEC 14443A/MIFARE Reader/Writer mode communication diagram .56 Fig 7. Data coding and framing according to ISO/IEC 14443A . . . . . . . . . . . . . . . . . . . . . . . . .57 Fig 8. ...
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... NXP Semiconductors 33. Contents 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 2 General description . . . . . . . . . . . . . . . . . . . . . . 1 3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 4 Quick reference data . . . . . . . . . . . . . . . . . . . . . 4 5 Ordering information . . . . . . . . . . . . . . . . . . . . . 4 6 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 5 7 Pinning information . . . . . . . . . . . . . . . . . . . . . . 7 7.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 7.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 8 8 PN512 register SET . . . . . . . . . . . . . . . . . . . . . 10 8.1 PN512 registers overview 8.1.1 Register bit behavior 8.2 Register description . . . . . . . . . . . . . . . . . . . . 13 8 ...
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... NXP Semiconductors 10.2.1 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 10.3 UART interface . . . . . . . . . . . . . . . . . . . . . . . . 66 10.3.1 Connection to a host controller . . . . . . . . . . . . 66 10.3.2 Selection of the transfer speeds . . . . . . . . . . . 67 10.3.3 Framing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . bus interface . . . . . . . . . . . . . . . . . . . . . . 70 10.4.1 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 10.4.2 Data validity . . . . . . . . . . . . . . . . . . . . . . . . . . 71 10.4.3 START and STOP conditions . . . . . . . . . . . . . 71 10.4.4 Byte format . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 10.4.5 Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . 72 10.4.6 7-bit addressing . . . . . . . . . . . . . . . . . . . . . . . 73 10.4.7 Register write access ...
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... NXP Semiconductors 24.1.8 Input pin characteristics for pin OSCIN 109 24.1.9 Output pin characteristics for pins AUX1 and AUX2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 24.1.10 Output pin characteristics for pins TX1 and TX2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 24.2 Current consumption . . . . . . . . . . . . . . . . . . 111 24.3 RX input voltage range . . . . . . . . . . . . . . . . . 111 24.4 RX input sensitivity . . . . . . . . . . . . . . . . . . . . 112 24 ...