PN5120A0HN1/C2,151 NXP Semiconductors, PN5120A0HN1/C2,151 Datasheet - Page 72

• Manufacturer Part Number: PN5120A0HN1/C2,151
• Description: IC TRANSMISSION MOD 32-HVQFN
• Manufacturer: NXP Semiconductors

Specifications of PN5120A0HN1/C2,151

• Rf Type: Read / Write
• Frequency: 13.56MHz
• Features: ISO14443-A, ISO14443-B
• Package / Case: 32-VFQFN Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

NXP Semiconductors
111334
Product data sheet
10.4.4 Byte format
10.4.5 Acknowledge
Each byte has to be followed by an acknowledge bit. Data is transferred with the MSB
first, see
unrestricted but shall fulfill the read/write cycle format.
An acknowledge at the end of one data byte is mandatory. The acknowledge-related clock
pulse is generated by the master. The transmitter of data, either master or slave, releases
the SDA line (HIGH) during the acknowledge clock pulse. The receiver shall pull down the
SDA line during the acknowledge clock pulse so that it remains stable LOW during the
HIGH period of this clock pulse.
The master can then generate either a STOP (P) condition to stop the transfer, or a
repeated START (Sr) condition to start a new transfer.
A master-receiver shall indicate the end of data to the slave- transmitter by not generating
an acknowledge on the last byte that was clocked out by the slave. The slave-transmitter
shall release the data line to allow the master to generate a STOP (P) or repeated
START (Sr) condition.
Fig 20. Acknowledge on the I
Fig 21. Data transfer on the I
Figure
22. The number of transmitted bytes during one data transfer is
Rev. 3.4 — 8 September 2009
2
2
C-bus
C- bus
Transmission Module
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