PN5120A0HN1/C2,151 NXP Semiconductors, PN5120A0HN1/C2,151 Datasheet - Page 92

• Manufacturer Part Number: PN5120A0HN1/C2,151
• Description: IC TRANSMISSION MOD 32-HVQFN
• Manufacturer: NXP Semiconductors

Specifications of PN5120A0HN1/C2,151

• Rf Type: Read / Write
• Frequency: 13.56MHz
• Features: ISO14443-A, ISO14443-B
• Package / Case: 32-VFQFN Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

NXP Semiconductors
14. Interrupt request system
111334
Product data sheet
14.1.1 Interrupt sources overview
14.1 Overview
The PN512 indicates certain events by setting bit IRq in the register Status1Reg and
additionally, if activated, by pin IRQ. The signal on pin IRQ may be used to interrupt the
host controller using its interrupt handling capabilities. This allows the implementation of
efficient host controller software.
The following table shows the available interrupt bits, the corresponding source and the
condition for its activation.
The interrupt bit TimerIRq in register CommIRqReg indicates an interrupt set by the timer
unit. The setting is done when the timer decrements from 1 to 0.
The TxIRq bit in register CommIRqReg indicates that the transmitter has finished. If the
state changes from sending data to transmitting the end of the frame pattern, the
transmitter unit sets the interrupt bit automatically.
The CRC co-processor sets the bit CRCIRq in the register DivIRqReg after having
processed all data from the FIFO-buffer. This is indicated by the bit CRCReady = 1.
The RxIRq bit in register CommIRqReg indicates an interrupt when the end of the
received data is detected.
The bit IdleIRq in register CommIRqReg is set if a command finishes and the content of
the command register changes to idle.
The bit HiAlertIRq in register CommIRqReg is set to logic 1 if the HiAlert bit is set to
logic 1, that means the FIFO-buffer has reached the level indicated by the bit WaterLevel.
The bit LoAlertIRq in register CommIRqReg is set to logic 1 if the LoAlert bit is set to
logic 1, that means the FIFO-buffer has reached the level indicated by the bit WaterLevel.
The bit RFOnIRq in register DivIRqReg is set to logic 1, when the RF level detector
detects an external RF field.
The bit RFOffIRq in register DivIRqReg is set to logic 1, when a present external RF field
is switched off.
The bit ErrIRq in register CommIRqReg indicates an error detected by the contactless
UART during sending or receiving. This is indicated by any bit set to 1 in register
ErrorReg.
The bit ModeIRq in register DivIRqReg indicates that the Data mode detector has
detected the Current mode.
Rev. 3.4 — 8 September 2009
Transmission Module
© NXP B.V. 2010. All rights reserved.
PN512
92 of 131
PUBLIC