PACCLK5406D-S-EVN Lattice, PACCLK5406D-S-EVN Datasheet - Page 19
PACCLK5406D-S-EVN
Manufacturer Part Number
PACCLK5406D-S-EVN
Description
Development Software ispClock5312S Eval 56020A Dev Mix Sig
Manufacturer
Lattice
Datasheet
1.PACCLK5406D-S-EVN.pdf
(42 pages)
Specifications of PACCLK5406D-S-EVN
Tool Type
Development Software Support
Core Architecture
CPLD
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lattice Semiconductor
5. Specify REF Frequency: 100 then click the Internal Feedback, Modify... button.
6. Select Internal Feedback, select Feedback taken from V-Divider 8, and click OK.
7. From the PLL Core Settings dialog, click OK.
8. From the Edit Symbol dialog, select USER PINS and click the Edit... button.
9. Select PLL_BYPASS = PLL then click the OK button.
10. From the Edit Symbol dialog select Output BANK_0 then click the Edit... button.
11. Click the Source, Modify... button.
12. For BANK_0, choose V-Divider-8, choose, From V-Divider, and click the OK button.
13. From the Edit Symbol dialog select Output BANK_2 then click the Edit... button.
14. From the Output Settings for BANK_2 & BANK_3 dialog, select the following options for BANK_2:
15. From the Edit Symbol dialog select Output BANK_4 then click the Edit... button.
16. From the Output Settings for BANK_4 & BANK_5 dialog, select the following options for BANK_4:
17. From the Edit Symbol dialog, click Close.
18. Click the Download icon on the top toolbar.
19. Click OK.
The External Feedback Setting dialog appears.
The USER Pin Function Allocation dialog appears.
The USER Pin Summary dialog appears. Click the OK button.
The Output Settings for BANK_0 & Bank_1 dialog appears.
The Output Pair Source Setting dialog box appears.
From the Output Settings for BANK_0 & BANK_1 dialog, select the following options for BANK_0:
Select the following option for BANK_1:
The Output Settings for BANK_2 & Bank_3 dialog appears.
Output Enable: Always Disabled
Select the following option for BANK_3:
Click the OK button.
The Output Settings for BANK_4 & Bank_5 dialog appears.
Select the following option for BANK_5:
Click the OK button.
The Frequency Summary dialog appears and reports the Reference and VCO frequency settings.
PAC-Designer reprograms the evaluation board with the updated JEDEC programming file.
Output Enable: Always Disabled
Output Enable: Always Disabled
Output Enable: Always Disabled
Output Type: LVPECL
Output Enable: Always Enabled
Output Enable: Always Disabled
Click the OK button.
19
ispClock5400D Evaluation Board
User’s Guide