PACCLK5406D-S-EVN Lattice, PACCLK5406D-S-EVN Datasheet - Page 9

• Manufacturer Part Number: PACCLK5406D-S-EVN
• Description: Development Software ispClock5312S Eval 56020A Dev Mix Sig
• Manufacturer: Lattice

Specifications of PACCLK5406D-S-EVN

• Tool Type: Development Software Support
• Core Architecture: CPLD
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Lattice Semiconductor
4. Position the mouse over the rising edge of the Bank2 Time waveform.
5. Click and hold the Bank 2 Time waveform, then drag it three units to the right.
6. Click the Write to Schematic button.
7. Click the Download icon on the top toolbar.
8. Click OK.
9. Note the updated scope display.
Figure 9. Scope Plot - De-skewed Outputs
The cursor will changes to a double-arrow icon to indicate a waveform edit.
The Setting field displays 3 and Time Skew (ps) displays 54.00.
PAC-Designer updates the time skew setting of the project.
The Frequency Summary dialog appears and reports the Reference and VCO frequency settings.
PAC-Designer reprograms the evaluation board with the updated JEDEC programming file.
This waveform shows the de-skewed outputs.
The programmable ispClock5406D Time Skew feature allows the device to account for very small incremental
delays and correct for system/board trace-level effects. The function is used to correct timing delays and line up
edges to either account for PCB layout or to help with clock system timing such as the set-up and hold times of
the circuit being driven.
Experiment with the Time Skew and visualize the results on the scope. The demo design time skew range
allows you to move clock edges from 18 ps to 270 ps. When finished, set back to the Time-Skew that yields the
best results for your set-up.
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ispClock5400D Evaluation Board
User’s Guide