EA-QSB-103 Embedded Artists, EA-QSB-103 Datasheet - Page 16

• Manufacturer Part Number: EA-QSB-103
• Description: MCU, MPU & DSP Development Tools QUICKSTART PROTOTYPE BRD W/ LPC2129 CAN
• Manufacturer: Embedded Artists

Specifications of EA-QSB-103

• Processor To Be Evaluated: LPC2129
• Data Bus Width: 16 bit, 32 bit
• Interface Type: RS-232, CAN, I2C, SPI, UART
• Core: ARM7TDMI-S
• Dimensions: 55 mm x 58 mm
• Maximum Operating Temperature: + 85 C
• Operating Supply Voltage: 5 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

NXP Semiconductors
Product data sheet
LPC2109_2119_2129_6
6.10.2 UART features available in LPC2109/2119/2129/01 only
6.11.1 Features
6.11 I
Compared to previous LPC2000 microcontrollers, UARTs in LPC2109/2119/2129/01
introduce a fractional baud rate generator for both UARTs, enabling these microcontrollers
to achieve standard baud rates such as 115200 Bd with any crystal frequency above
2 MHz. In addition, auto-CTS/RTS flow-control functions are fully implemented in
hardware.
The I
line (SCL), and a serial data line (SDA). Each device is recognized by a unique address
and can operate as either a receiver-only device (e.g. an LCD driver or a transmitter with
the capability to both receive and send information (such as memory). Transmitters and/or
receivers can operate in either master or slave mode, depending on whether the chip has
to initiate a data transfer or is only addressed. The I
controlled by more than one bus master connected to it.
The I
I
2
2
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C-bus).
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•
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•
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C-bus serial I/O controller
UART1 is equipped with standard modem interface signals. This module also
provides full support for hardware flow control (auto-CTS/RTS).
Fractional baud rate generator enables standard baud rates such as 115200 Bd to be
achieved with any crystal frequency above 2 MHz.
Auto-bauding.
Auto-CTS/RTS flow-control fully implemented in hardware.
Standard I
Easy to configure as Master, Slave, or Master/Slave.
Programmable clocks allow versatile rate control.
Bidirectional data transfer between masters and slaves.
Multi-master bus (no central master).
Arbitration between simultaneously transmitting masters without corruption of serial
data on the bus.
Serial clock synchronization allows devices with different bit rates to communicate via
one serial bus.
Serial clock synchronization can be used as a handshake mechanism to suspend and
resume serial transfer.
The I
2
2
C-bus implemented in LPC2109/2119/2129 supports a bit rate up to 400 kbit/s (Fast
C-bus is a bidirectional bus for inter-IC control using only two wires: a serial clock
2
C-bus may be used for test and diagnostic purposes.
2
C-bus compliant interface.
Rev. 06 — 10 December 2007
LPC2109/2119/2129
Single-chip 16/32-bit microcontrollers
2
C-bus is a multi-master bus; it can be
© NXP B.V. 2007. All rights reserved.
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