P0071 Terasic Technologies Inc, P0071 Datasheet - Page 33

• Manufacturer Part Number: P0071
• Description: TPAD MULTIMEDIADEVELOPMENT KIT
• Manufacturer: Terasic Technologies Inc
• Series: tPAD, Cyclone®IVr

Specifications of P0071

• Main Purpose: Reference Design, Tablet
• Embedded: Yes, FPGA / CPLD
• Utilized Ic / Part: EP4CE115
• Primary Attributes: 8-Inch TFT LCD, LED Backlight
• Secondary Attributes: 5-Megapixel Digital Image Sensor
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

These functions allow you to fully integrate common video functions with video interfaces,
processors, and external memory controllers. The example design uses an Altera Cyclone® IV E
EP4CE115F29 featured tPad board.
A video source is input through the CMOS sensor on tPad which generates a digital output in RGB
format. A number of common video functions are performed on this input stream in the FPGA.
These functions include clipping, chroma resampling, motion adaptive deinterlacing, color space
conversion, picture-in-picture mixing, and polyphase scaling.
The input and output video interfaces on the tPad are configured and initialized by software running
on a Nios® II processor. Nios II software demonstrates how to control the clocked video input,
clocked video output, and mixer functions at run-time is also provided. The video system is
implemented using the SOPC Builder system level design tool. This abstracted design tool provides
an easy path to system integration of the video processing data path with a NTSC or PAL video
input, VGA output, Nios II processor for configuration and control. The Video and Image
Processing Suite MegaCore functions have common open Avalon-ST data interfaces and Avalon
Memory-Mapped (Avalon-MM) control interfaces to facilitate connection of a chain of video
functions and video system modeling. In addition, video data is transmitted between the Video and
Image Processing Suite functions using the Avalon-ST Video protocol, which facilitates building
run-time controllable systems and error recovery.
For the objective of a better visual effect, the CMOS sensor is configured to enable the left right
mirror mode. User could disable this functionality by modifying the related register value being
written to CMOS controller chip.
Figure 4-14
shows the Video and Image Processing block diagram.
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