LFE2-50E-H-EV Lattice, LFE2-50E-H-EV Datasheet - Page 110

• Manufacturer Part Number: LFE2-50E-H-EV
• Description: MCU, MPU & DSP Development Tools LatticeECP2 Eval Brd - Advanced
• Manufacturer: Lattice

Specifications of LFE2-50E-H-EV

• Processor To Be Evaluated: LatticeECP2 FPGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Lattice Semiconductor
LatticeECP2 Pin Information Summary, LFE2-20 and LFE2-35
Single Ended User I/O
Differential Pair User I/O
Configuration
Non Configuration
VCC
VCCAUX
VCCPLL
VCCIO
GND, GND0 to GND7
NC
Single Ended/ Differential I/O
Pairs per Bank (including 
emulated with resistors)
True LVDS I/O Pairs per Bank
Pin Type
TAP Pins
Muxed Pins
Dedicated Pins (Non TAP)
Muxed Pins
Dedicated Pins
Bank0
Bank1
Bank2
Bank3
Bank4
Bank5
Bank6
Bank7
Bank8
Bank0
Bank1
Bank2
Bank3
Bank4
Bank5
Bank6
Bank7
Bank8
Bank0 (Top Edge)
Bank1 (Top Edge)
Bank2 (Right Edge)
Bank3 (Right Edge)
Bank4 (Bottom Edge)
Bank5 (Bottom Edge)
Bank6 (Left Edge)
Bank7 (Left Edge)
Bank8 (Right Edge)
4-7
PQFP
18/9
18/9
11/5
11/5
19/9
18/9
18/8
12/6
208
131
6/2
14
42
14
22
62
5
7
3
8
0
2
2
2
2
2
2
2
2
2
0
0
0
4
3
0
0
6
5
0
fpBGA
34/17
20/10
32/16
26/13
20/10
18/9
12/6
17/8
14/7
256
193
96
14
54
20
5
7
3
7
4
0
2
2
2
2
2
2
2
2
1
1
0
0
5
3
0
0
7
5
0
LFE2-20
LatticeECP2/M Family Data Sheet
fpBGA
50/25
46/23
34/17
22/11
46/23
46/23
40/20
33/16
14/7
484
331
165
14
60
18
16
60
10
5
7
3
0
4
4
4
4
4
4
4
4
2
8
0
0
9
5
0
0
8
0
fpBGA
67/33
52/26
36/18
32/16
50/25
68/34
48/24
35/17
14/7
672
402
200
101
14
64
24
16
72
12
5
7
3
0
5
5
5
5
5
5
5
5
2
0
0
9
8
0
0
8
0
Pinout Information
fpBGA
50/25
46/23
34/17
22/11
46/23
46/23
40/20
33/16
14/7
484
331
165
14
60
16
16
60
10
5
7
3
2
4
4
4
4
4
4
4
4
2
8
0
0
9
5
0
0
8
0
LFE2-35
fpBGA
67/33
52/26
48/24
42/21
54/27
68/34
58/29
47/23
14/7
672
450
224
102
14
68
22
16
72
12
13
11
5
7
3
2
5
5
5
5
5
5
5
5
2
0
0
9
0
0
0