LFE2-50E-H-EV Lattice, LFE2-50E-H-EV Datasheet - Page 41

• Manufacturer Part Number: LFE2-50E-H-EV
• Description: MCU, MPU & DSP Development Tools LatticeECP2 Eval Brd - Advanced
• Manufacturer: Lattice

Specifications of LFE2-50E-H-EV

• Processor To Be Evaluated: LatticeECP2 FPGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Lattice Semiconductor
Figure 2-35. Edge Clock, DLL Calibration and DQS Local Bus Distribution
Spans 16 PIOs
Spans 18 PIOs
DQS Input
Note: Bank 8 is not shown.
I/O
I/O
B
a
n
7
B
a
n
6
k
k
DDR_DLL
I/O Bank 5
(Left)
I/O Bank 0
2-38
I/O Bank 4
I/O Bank 1
DDR_DLL
(Right)
LatticeECP2/M Family Data Sheet
I/O
I/O
B
B
a
n
k
2
a
n
k
3
ECLK1
ECLK2
Delayed
DQS
Polarity Control
DQSXFER
DQS Delay
Control Bus
Architecture