LFE2-50E-H-EV Lattice, LFE2-50E-H-EV Datasheet - Page 26

• Manufacturer Part Number: LFE2-50E-H-EV
• Description: MCU, MPU & DSP Development Tools LatticeECP2 Eval Brd - Advanced
• Manufacturer: Lattice

Specifications of LFE2-50E-H-EV

• Processor To Be Evaluated: LatticeECP2 FPGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Lattice Semiconductor
MULT sysDSP Element
This multiplier element implements a multiply with no addition or accumulator nodes. The two operands, A and B,
are multiplied and the result is available at the output. The user can enable the input/output and pipeline registers.
Figure 2-23 shows the MULT sysDSP element.
Figure 2-23. MULT sysDSP Element
Multiplicand
Multiplier
Signed A
Signed B
Shift Register B Out
Shift Register B In
n
Input Data
Register B
n
n
n
Register
Register
Input
Input
m
Register A
Input Data
m
m
Shift Register A Out
m
Shift Register A In
2-23
Multiplier
Multiplier
m
n
To
To
Multiplier
Register
Pipeline
x
CLK (CLK0,CLK1,CLK2,CLK3)
CE (CE0,CE1,CE2,CE3)
RST(RST0,RST1,RST2,RST3)
LatticeECP2/M Family Data Sheet
(default)
m+n
m+n
Output
Architecture