LC5512M-PAC-EV Lattice, LC5512M-PAC-EV Datasheet - Page 22

• Manufacturer Part Number: LC5512M-PAC-EV
• Description: MCU, MPU & DSP Development Tools Eval Board for XPLD5512 PAC1208
• Manufacturer: Lattice

Specifications of LC5512M-PAC-EV

• Processor To Be Evaluated: ispXPLD 5512MX
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Lattice Semiconductor
Figure 17. I/O Cell
Table 10. Shared PTOE Segments
sysIO Standards
Each I/O within a bank is individually configurable based on the V
require the use of an external termination voltage. Table 12 lists the sysIO standards with the typical values for
V
Lattice
Table 11. Number of I/Os per Bank
CCO,
V
Devices.
REF
and V
TT.
For more information on the sysIO capability, refer to TN1000,
ispXPLD 5256MX
ispXPLD 5512MX
ispXPLD 5768MX
ispXPLD 51024MX
ispXPLD 5256MX
ispXPLD 5512MX
ispXPLD 5768MX
ispXPLD 51024MX
Device
Device
Maximum Number of I/Os per Bank (n)
MFBs Associated With Segments
(Y, Z, AA, AB) (AC, AD, AE, AF)
18
(Q, R, S, T) (U, V, W, Z)
(Q, R, S, T) (U, V, W, Z)
(A, B, C, D) (E, F, G, H)
(A, B, C, D) (E, F, G, H)
(A, B, C, D) (E, F, G, H)
(A, B, C, D) (E, F, G, H)
(I, J, K, L) (M, N, O, P)
(I, J, K, L) (M, N, O, P)
(I, J, K, L) (M, N, O, P)
36
68
96
96
CCO
ispXPLD 5000MX Family Data Sheet
and V
REF
settings. Some standards also
sysIO Usage Guidelines for