CorePCI Eval Board Actel, CorePCI Eval Board Datasheet - Page 10

• Manufacturer Part Number: CorePCI Eval Board
• Description: MCU, MPU & DSP Development Tools CorePCI v5.41
• Manufacturer: Actel

Specifications of CorePCI Eval Board

• Processor To Be Evaluated: SX-A device
• Interface Type: RS-232

Table 6 • CorePCI Backend Interface Signal (Continued)
1 0
Name
WR_BE_NOW[3:0]
WR_BE_NOW64[3:0]
WR_BE_RDY
PIPE_FULL_CNT[2:0] Input
BE_REQ
BE_GNT
DMA_GNT
BUSY_MASTER
STALL_MASTER
ERROR
Notes:
1. Active LOW signals are designated with a trailing lower-case n.
2. Signals ending in "CYC" become valid as the same cycle DP_START is active and will remain valid throughout the current cycle (until
3. MADDR_WIDTH is defined in
4. All inputs should be synchronous to the PCI clock.
CorePCI v5.41
DP_DONE is asserted).
1,2
Type
Output
Input
Output
Input
Input
Input
Input
Output
Table 22 on page
Description
Active high synchronous write strobe. These signals indicate that the PCI controller is providing
valid write data on the MEM_DATA bus. These signals are active whenever both the backend
(as indicated by WR_BE_RDY) and the PCI bus (as indicated by IRDYn) are ready to transmit
data. The WR_BE_NOW indicates a write from the lower 32 bits of data and the
WR_BE_NOW64 indicates a write from the upper 32 bits of data. For WR_BE_NOW, each bit
represents a byte enable with bit 0 corresponding to the least significant byte (byte 0) on the
MEM_DATA bus. Similarly, for WR_BE_NOW64, each bit represents a byte enable with bit 0
corresponding to byte 4 on the MEM_DATA bus. Function of these signals are impacted by the
PIPE_FULL_CNT bus
Active high signal indicating that the backend is ready to receive data from the Target
interface. If the ready signal does not become active within the time limits defined by the PCI
bus, then a disconnect without data will be initiated.
Normally, the address on MEM_ADDRESS and the data on MEM_DATA are coincident. In some
backends, like synchronous SRAMs, the data lags the address by one or more cycles. The
PIPE_FULL_CNT bus feeds a latency timer in the PCI controller to help in these cases. When the
PIPE_FULL_CNT is non-zero, the PCI controller will increment the address, the number of
counts defined and will not expect data until the count expires. The RD_BE_NOW and
WR_BE_NOW signals need to be ignored during the time-out. For example, if PIPE_FULL_CNT
is set to '010', then the *_NOW signals should be ignored during the first two cycles they are
active, while the address is initially incremented.
A request from the backend to the PCI Controller to take control of the backend. This signal is
active high, and should be synchronous to the PCI clock.
A grant from the PCI Controller giving control to the backend. When the BE_GNT signal is
active and a transaction to the PCI Target controller occurs, the PCI controller will respond with
a Retry cycle. If a cycle is in progress when the BE_REQ is asserted, the BE_GNT will not assert
until completion of the current PCI cycle. If the backend must take control during a cycle, then
the ready signals can be de-asserted, causing a PCI time-out and resulting disconnect.
Indicates that the internal DMA controller has control of the back-end core interface.
When high DMA cycles will not be started. If a DMA-cycle is in progress and this signal goes
high the DMA cycle will be stopped within two data transfers, i.e. up to two more data cycles
may occur when the signal goes high.
If high when CorePCI starts a DMA cycle
hold off asserting FRAME and starting the cycle on the PCI bus until STALL_MASTER
is deasserted (low) signifying that the back end's data is now ready. This can be used
to support backends that take several cycles to become ready. Note that GNT can be
removed at anytime while the core is waiting for the backend data, which will cause
the core to abort the cycle.
Active high signal that will force the PCI controller to terminate the current transfer with a
Target abort cycle. The signal affects the Target function only, it is ignored during master
operation.
20.
(Figure
v4.0
15).
on the backend, it will assert DP_START, but