CorePCI Eval Board Actel, CorePCI Eval Board Datasheet - Page 28

• Manufacturer Part Number: CorePCI Eval Board
• Description: MCU, MPU & DSP Development Tools CorePCI v5.41
• Manufacturer: Actel

Specifications of CorePCI Eval Board

• Processor To Be Evaluated: SX-A device
• Interface Type: RS-232

Paced Transactions
Backend
mechanism for supporting slow response devices. The
backend transactions are paced using the RD_BE_RDY
and WR_BE_RDY signals. These signals can be used to
pace either single DWORD or burst transactions.
Notes:
1. The WR_BE_RDY can be asserted two cycles before the backend is ready to receive data.
2. The WR_BE_RDY signal is asserted on cycle 4 (cycle 7), causing the assertion of TRYDYn on cycle 5 (cycle 8), completing the PCI write
3. The WR_BE_NOW[3:0] should not be assumed to happen at this time (cycle 6 or cycle 9) because it is also dependent on the state of
4. See
Figure 11 • Write Using Backend Throttling
2 8
CorePCI v5.41
cycle. One cycle later, the data is available on the backend and is qualified by the WR_BE_NOW[3:0] bus.
IRDYn.
Figure 7 on page 24
throttle
MEM_ADDRESS[23:2]
MEM_DATA[31:0]
WR_BE_NOW
transfers
WR_BE_RDY
DP_START
DP_DONE
AD[31:0]
DEVSELn
FRAMEn
for WR_CYC and BARn_CYC timing.
CBE[3:0]
TRDYn
STOPn
IRDYn
PAR
CLK
provide
1
addr
0111
a
2
handshake
Paddr
3
data0
4
v4.0
Pdata0
Figure 11
mechanism for a backend that requires three cycles to
respond to a read or write command from the PCI
bus.
5
byte enables
add0
6
data0
and
7
data1
Figure 12 on page 29
8
Pd1
add1
9
data1
10
11
12
illustrate this