CorePCI Eval Board Actel, CorePCI Eval Board Datasheet - Page 9

• Manufacturer Part Number: CorePCI Eval Board
• Description: MCU, MPU & DSP Development Tools CorePCI v5.41
• Manufacturer: Actel

Specifications of CorePCI Eval Board

• Processor To Be Evaluated: SX-A device
• Interface Type: RS-232

Table 6 • CorePCI Backend Interface Signal
Name
CLK_OUT
BAR0_MEM_CYC
BAR1_CYC
CONFIG_CYC
RD_CYC
WR_CYC
MEM_DIN
MEM_DOUT
MEM_DATA_DEN
MEM_DATA_DEN64 Output
MEM_ADD[N:0]
DP_START
DP_START64
DP_DONE
RD_BE_NOW
RD_BE_NOW64
RD_BE_RDY
Notes:
1. Active LOW signals are designated with a trailing lower-case n.
2. Signals ending in "CYC" become valid as the same cycle DP_START is active and will remain valid throughout the current cycle (until
3. MADDR_WIDTH is defined in
4. All inputs should be synchronous to the PCI clock.
DP_DONE is asserted).
1,2
3
Type
Output
Output
Output
Output
Input
Output
Output
Output
Output
Output
Output
Input
Output
Output
Table 22 on page
Description
Clock Output. The core uses an internal clock buffer, this is buffered version of the clock and
should be used for clocking any other logic in the FPGA that is clocked by the PCI clock.
Active high signal indicating a transaction to the memory space defined in the base address
register zero (BAR0) located at 10H in Configuration Header Space.
Active high signal indicating a transaction to the optional memory or I/O space defined in base
address register one (BAR1) located at 14H in Configuration Header Space.
Active high signal indicating a transaction to configuration space.
Active high signal indicating a read transaction from the backend.
Active high signal indicating a write transaction to the backend.
DWORD aligned 32- or 64-bit databus input
DWORD aligned 32- or 64-bit databus output
Active high data enable for MEM_DOUT, lower 32-bit. This is intended as an output enable if
MEM_DIN and MEM_DOUT are connected to bi-directional pads.
Active high data enable for MEM_DOUT, upper 32-bit. This is intended as an output enable if
MEM_DIN and MEM_DOUT are connected to bi-directional pads.
DWORD aligned memory address bus where N is defined by the variable MADDR_WIDTH.
Since the PCI address is byte aligned, a 2-bit shift of the address is performed and PCI address
bits 0 and 1 are discarded. For example, a 1 Mbyte memory requires 20 address bits to
uniquely address each byte or 18 address bits to uniquely address each DWORD. A PCI address
of 'CCCCC'h would translate to '33333'h on the backend. For writes, individual bytes are
qualified with the 4-bit WR_BE_NOW bus. All reads are assumed to be full DWORDS.
DP_START is an active high pulse indicating that a PCI transaction to the backend is beginning.
If the transfer is 64-bit, then DP_START64 will be asserted at the same time as DP_START.
Active high pulse indicating that a successful PCI transaction to the backend has finished.
Active High Synchronized Read Strobe. When active high, these signals indicate that the PCI
controller will read data on the MEM_DATA bus on the next rising clock edge. These signals
are active whenever both the backend (as indicated by RD_BE_RDY) and the PCI bus (as
indicated by IRDYn) are ready to transmit data. The RD_BE_NOW indicates a write to the lower
32 bits of data and the RD_BE_NOW64 indicates a read from the upper 32 bits of data.
Function of these signals are impacted by the PIPE_FULL_CNT bus
Active high signal indicating that the backend is ready to send data to the Target interface. If
the ready signal does not become active within the limits defined by the PCI bus, then a
disconnect without data will be initiated.
20.
v4.0
(Figure
15).
CorePCI v5.41
9