CorePCI Eval Board Actel, CorePCI Eval Board Datasheet - Page 25

• Manufacturer Part Number: CorePCI Eval Board
• Description: MCU, MPU & DSP Development Tools CorePCI v5.41
• Manufacturer: Actel

Specifications of CorePCI Eval Board

• Processor To Be Evaluated: SX-A device
• Interface Type: RS-232

Notes:
1. When FRAMEn is asserted and the command bus is '0110', then a read from memory space is indicated.
2. The Target will compare the address to the programmed space set in the memory base address register.
3. If an address hit occurs, then the Target asserts DP_START in cycle 3 and claims the PCI bus by asserting DEVSELn in cycle 4.
4. Data transfer from the backend begins on the rising edge of cycle 7 and continues for each subsequent cycle until the PCI bus ends
5. The address will increment each cycle following an active RD_BE_NOW.
6. The PCI transaction completes when TRDYn is de-asserted in cycle 10.
7. For this case, the PIPE_FULL_CNT is set to "000" (See
Figure 8 • 32-Bit Burst Read with Zero Wait States
the data transfer. The backend prefetches three DWORDs during zero-wait-state bursts.
MEM_ADDRESS
RD_BE_NOW
MEM_DATA
RD_BE_RDY
BARn_CYC
DP_START
DP_DONE
DEVSELn
FRAMEn
RD_CYC
TRDYn
STOPn
IRDYn
CLK
PAR
CBE
AD
1
0110
addr
2
Paddr
3
"Backend Latency Control" on page 31
4
v4.0
5
add0
data0
byte enables
6
data0
data1
add1
7
data1
data2
add2
Pd0
8
data2
data3
add3
Pd1
9
data3
for more information).
add4
data4
Pd2
10
data5
add5
Pd3
11
12
CorePCI v5.41
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