MEDIA5200KIT1 Freescale Semiconductor, MEDIA5200KIT1 Datasheet - Page 18

• Manufacturer Part Number: MEDIA5200KIT1
• Description: MCU, MPU & DSP Development Tools MEDIA5200 SW DEVT SYSTEM
• Manufacturer: Freescale Semiconductor

Specifications of MEDIA5200KIT1

• Processor To Be Evaluated: MPC5200B
• Data Bus Width: 32 bit
• Interface Type: Ethernet, USB
• Lead Free Status / Rohs Status: Not Compliant

1.3.6.2
In Standard SDRAM, all signals are activated on the MEM_CLK from the Memory Controller and captured on the MEM_CLK
clock at the memory device.
18
data
t
data
DM
DM
mem_clk
MBA (Bank Selects)
Sym
t
t
valid
hold
DQM (Data Mask)
valid
hold
valid
hold
Control Signals
MA (Address)
NOTE: Control Signals are composed of RAS, CAS, MEM_WE, MEM_CS, MEM_CS1 and CLK_EN
MDQ (Data)
MEM_CLK
Memory Interface Timing-Standard SDRAM Write Command
Control Signals, Address and MBA Hold after
DQM valid after rising edge of MEM_CLK
MDQ valid after rising edge of MEM_CLK
MDQ hold after rising edge of MEM_CLK
Control Signals, Address and MBA Valid
DQM hold after rising edge of Mem_clk
Figure 5. Timing Diagram—Standard SDRAM Memory Read Timing
after rising edge of MEM_CLK
rising edge of MEM_CLK
MEM_CLK period
t
t
t
valid
valid
Description
valid
Table 19. Standard SDRAM Write Timing
Active
Row
t
hold
DM
valid
MPC5200B Data Sheet, Rev. 4
t
t
hold
hold
NOP
Column
READ
t
t
mem_clk
mem_clk
t
mem_clk
DM
data
Min
× 0.25 – 0.7
× 0.75 – 0.7
7.5
NOP
—
—
—
hold
× 0.5
setup
NOP
t
t
t
mem_clk
mem_clk
mem_clk
data
NOP
Max
× 0.25 + 0.4
× 0.75 + 0.4
—
× 0.5 + 0.4
—
—
—
hold
NOP
Freescale Semiconductor
Units
ns
ns
ns
ns
ns
ns
ns
NOP
SpecID
A5.10
A5.11
A5.12
A5.13
A5.14
A5.8
A5.9