LS-E2-L-BASE-PC-N Lattice, LS-E2-L-BASE-PC-N Datasheet
LS-E2-L-BASE-PC-N
Specifications of LS-E2-L-BASE-PC-N
Related parts for LS-E2-L-BASE-PC-N
LS-E2-L-BASE-PC-N Summary of contents
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... LatticeECP2™ Standard Evaluation Board User’s Guide May 2007 Revision: ebdug18_01.3 ...
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... Lattice Semiconductor Introduction The LatticeECP2 Standard Evaluation Board is a complete, integrated design, featuring a LatticeECP2 FPGA and a variety of both application-specific and general-purpose peripheral interfaces. This board provides a convenient platform to evaluate, test, and debug user designs, including designs requiring PCI/PCI-X. This board includes the following features: • ...
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... LatticeECP2 pin J21 (this is the default position). When pin 1 of the oscilla- tor is aligned to pin 2 of the socket, the clock is routed to LatticeECP2 pin J21. When using a half size oscillator, align pin 1 of the oscillator to pin 1 of the socket to drive the primary clock, or align pin 1 of the oscillator to pin 5 of the socket to drive the PLL ...
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... The JTAG connector is a 1x10 header and the sysCONFIG connector is a 2x17 header. Both the JTAG and the sysCONFIG ports are also provided with loop-through connectors to allow for easy daisy chaining of multiple boards. With proper jumper selection (see the next section) standard IDC ribbon cable can be used without the need to swap wires on the cable. See the Confi ...
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... Table 4. sysCONFIG Loop-Through Header Pinout (J41) Function CCLK N/C DOUT / CSSON N/C DONE CSN / N/C CS1N / N/C N/C Ground 1. See section below on jumpers. JTAG and sysCONFIG Jumpers There are several JTAG and sysCONFIG cabling options that can be selected using jumpers. LatticeECP2 Standard Evaluation Board Pin ...
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... Lattice Semiconductor Default Jumpers Settings This table lists the default settings for all of the jumpers on the LatticeECP2 Standard Evaluation Board. For a com- plete description of each jumper refer to the next sections. Table 5. Default Jumper Settings Location J10 J11 J13 J17 J18 J19 ...
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... Function Pulls CS1N high Pulls CS1N low No pull-up or pull-down on CS1N Function Pulls CSN high Pulls CSN low No pull-up or pull-down on CSN Function Routes DI to J40-5 to support serial mode Routes data bit D[0] to J40-5 for SPIFAST support Function Routes D[7] to J40-7 for SPI sysCONFIG support ...
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... J34 J43 J44 J35, J36 J35, J36 Table 19. Jumper Settings for sysCONFIG Serial Location J31 J32 J33 J34 J43 J44 J35, J36 J35, J36 LatticeECP2 Standard Evaluation Board CFG[2], CFG[1 Jumper (0) Jumper (0) Jumper (0) Jumper (0) Jumper (0) Open (1) Jumper (0) Open (1) Open (1) Jumper (0) Open (1) ...
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... The header at J29 allows a current measuring device to be inserted between 3.3V and the FPGA’s V measure current, remove power from the board, remove the jumper at J29, install a meter between pins 1 and 2, and apply power to the board. When measurement is complete, remove power from the board and re-install the jumper. LatticeECP2 Standard Evaluation Board Position Open Open ...
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... Note that if the LatticeECP2 will be configured from the SPI Serial Flash, bank 8 must be set to 3.3V (because SPI Serial Flash is 3.3V). Also, if the board is plugged into a PCI/PCI-X connector, bank 6 must be set to 3.3V (because the PCI clock is routed to bank 6 on this board). ...
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... Available on 50% of the I/Os in the Bank. PCI/PCI-X The LatticeECP2 Standard Evaluation Board is designed to be compatible with PCI (PCI SIG 2.2 specification) and PCI-X (Mode 1). All necessary signals required for 64-bit PCI/PCI-X operation are provided, as shown in Table 27 and Table 28. Table 27. PCI Connections - Solder Side ...
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... GND 25 PCI_AD24 26 PCI_IDSEL 27 +3.3V 28 PCI_AD22 29 PCI_AD20 30 GND 31 PCI_AD18 32 PCI_AD16 33 +3.3V 34 PCI_FRAME_N 35 GND 36 PCI_TRDY_N 37 GND 38 PCI_STOP_N 39 +3.3V 40 PCI_SMBCLK 41 PCI_SMBDAT 42 GND 43 PCI_PAR 44 PCI_AD15 45 +3.3V 46 PCI_AD13 47 PCI_AD11 48 GND 49 PCI_AD9 52 PCI_CBE0_N 53 +3.3V 54 PCI_AD6 55 PCI_AD4 LatticeECP2 Standard Evaluation Board LatticeECP2 Pin sysIO Bank - - U10 V10 W10 5 ...
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... GND 79 PCI_AD48 80 PCI_AD46 81 GND 82 PCI_AD44 83 PCI_AD42 84 +3.3V 85 PCI_AD40 86 PCI_AD38 87 GND 88 PCI_AD36 89 PCI_AD34 90 GND 91 PCI_AD32 GND 94 NC Note pull-down resistor pull-up resistor no-connect test point. LatticeECP2 Standard Evaluation Board LatticeECP2 Pin sysIO Bank - - W13 4 U14 W14 V14 4 U15 T15 4 Y15 W15 4 U16 ...
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... PCI_AD29 22 GND 23 PCI_AD27 24 PCI_AD25 25 3.3V 26 PCI_CBE3_N 27 PCI_AD23 28 GND 29 PCI_AD21 30 PCI_AD19 31 3.3V 32 PCI_AD17 33 PCI_CBE2_N 34 GND 35 PCI_IRDY_N 36 +3.3V 37 PCI_DEVSEL_N 38 PCIXCAP 39 LOCK# 40 PCI_PERR_N 41 +3.3V 42 PCI_SERR_N 43 +3.3V 44 PCI_CBE1_N 45 PCI_AD14 46 GND LatticeECP2 Standard Evaluation Board LatticeECP2 Pin sysIO Bank - - - - - - - - - - - - - - - - J14 - AB2 5 AA3 AB3 5 AB4 AA5 5 AB5 ...
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... PCI_AD59 72 PCI_AD57 73 GND 74 PCI_AD55 75 PCI_AD53 76 GND 77 PCI_AD51 78 PCI_AD49 79 +3.3V 80 PCI_AD47 81 PCI_AD45 82 GND 83 PCI_AD43 84 PCI_AD41 85 GND 86 PCI_AD39 87 PCI_AD37 88 +3.3V 89 PCI_AD35 90 PCI_AD33 91 GND 92 NC LatticeECP2 Standard Evaluation Board LatticeECP2 Pin sysIO Bank AB10 5 AA11 AB11 5 Y11 AB12 5 AA12 AB13 AA13 AB14 5 AA14 AB15 4 ...
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... PCI/PCI-X Jumpers Table 29. PRSNT1 Location Position Open Not installed. If installing header, first cut trace between 2 and 3. If master, also install R51 and C39. Table 30. PRSNT2 Location Position J23 Open Not installed. If master, also install R62 and C47. Table 31. PCIXCAP and M66EN Encoding ...
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... This board supports testing of single-ended and differential signals. High-Speed Single-Ended There are eight FPGA signals that have been routed to special test points on the board. Each signal can include a series resistor, as well as a pull-up resistor and a pull-down resistor (for maximum flexibility these resistors are not included with the board). Each series resistor footprint has a shorting trace that must be cut before installing a resistor (see Figure 3). Next to each signal’ ...
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... By default these resistors are not installed on the board. Switches Switch 1 (SW1) on the top edge of the board is an eight-switch block that is part of the prototyping area. A switch in the down position produces a low (logic 0), while the up position produces a high (logic 1). All SW1 signals go to bank 1. LatticeECP2 Standard Evaluation Board ...
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... Eight user-definable LEDs are provided on the top of the board under SW1. These LEDs are each wired to a sepa- rate GPIO on bank 1 as defined in the Table 39. The current limiting resistors associated with these LEDs are wired to 3.3V, but it is safe to drive these signals with any FPGA I/O voltage. The LED will light when its associated I/O pin is driven low. ...
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... Figure 4. Seven-Segment Display LCD Connector The LCD Connector has 18 pins, but only 16 are required for simple LCD panels. If using an OPTREX 51505 or equivalent, use pins 1-16, if using a LUMEX LCM-S02002DSR or equivalent, use pins 3-18. Two potentiometers are provided for LCD control. R34 adjusts the backlight and R35 adjusts the contrast. Power for the LCD panel is provided by the 3 ...
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... D03 2 D04 3 D05 4 D06 5 D07 6 CE1 7 A10 A09 10 A08 11 A07 12 3.3V 13 A06 14 A05 15 A04 16 A03 17 A02 18 A01 19 LatticeECP2 Standard Evaluation Board J42 Signal 1 Anode (R34) 2 Cathode (GND) 3 VSS (GND) 4 VDD (5V (R35 R DB0 10 DB1 11 DB2 12 DB3 13 DB4 14 DB5 15 DB6 16 DB7 17 Anode (R34) ...
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... TN1108, LatticeECP2 sysCONFIG Usage Guide. SRAM Configuration The LatticeECP2 SRAM can be configured easily via the JTAG port. The LatticeECP2 device is SRAM-based must remain powered to retain its configuration when programming just the SRAM. To program the SRAM, perform the following procedure: 1 ...
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... Important Note: The board must be un-powered when connecting, disconnecting, or reconnecting the isp- DOWNLOAD Cable. Always connect the ispDOWNLOAD Cable's GND pin (black wire), before connecting any other JTAG pins. Failure to follow these procedures can in result in damage to the LatticeECP2 FPGA device and render the board inoperable. ...
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... Install all three jumpers at J43, and the jumper at J44. This enables SPI mode by setting the CFG pins of the LatticeECP2, and it enables fast SPI reads. Check that J7 and J8 are properly set (see Table 6 and Table 7), and that J10 and J11 are open. ...
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... Base with LatticeECP2 50E Standard Development Kit Technical Support Assistance Hotline: 1-800-LATTICE (North America) +1-503-268-8001 (Outside North America) e-mail: techsupport@latticesemi.com Internet: www.latticesemi.com LatticeECP2 Standard Evaluation Board Ordering Part China RoHS Environment- Number Friendly Use Period (EFUP) LFE2-50E-L-EV LS-E2-L-BASE-PC-N 25 User’s Guide 10 ...
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... April 2007 May 2007 © 2007 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. ...
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... Lattice Semiconductor Appendix A. Schematics Figure 8. Block Diagram LatticeECP2 Standard Evaluation Board 27 User’s Guide ...
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... Lattice Semiconductor Figure 9. LCD, CF, RS-232, LEDs LatticeECP2 Standard Evaluation Board 9) DP(Pin 12) B(Pin 10) C(Pin 2) F(Pin 7) E(Pin Backlight CF_CD2 CF_CD1 CF_WAIT CF_READY CF_WP CF_INPACK CF_VS2 CF_VS1 CF_BVD2 CF_BVD1 28 User’s Guide ...
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... Lattice Semiconductor Figure 10. Prototyping Area GND LatticeECP2 Standard Evaluation Board (Default) Group Group DQS DQS Group Group DQS DQS 29 User’s Guide ...
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... Lattice Semiconductor Figure 11. 64-Bit PCI, PCI-X DQS Group DQS Group DQS Group DQS Group Group Group DQS DQS LatticeECP2 Standard Evaluation Board PAR64 PCI_CBE5_N PCI_CBE7_N PCI_REQ64_N PCI_CBE0_N DQS Group DQS Group PCI_PAR Group Group DQS DQS PCI_SMBDAT Group Group DQS DQS ...
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... Lattice Semiconductor Figure 12. SI Testing 2 DQS Group DQS Group Group Group DQS DQS LatticeECP2 Standard Evaluation Board DQS Group DQS Group Group Group DQS DQS SI[7:0] 31 User’s Guide GND GND ...
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... Lattice Semiconductor Figure 13. JTAG and sysCONFIG LatticeECP2 Standard Evaluation Board VCCJ VCCJ User’s Guide ...
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... Lattice Semiconductor Figure 14. FPGA Power LatticeECP2 Standard Evaluation Board User’s Guide ...
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... Lattice Semiconductor Figure 15. Power T520B476M006ASE070 protection polarity Reverse LatticeECP2 Standard Evaluation Board User’s Guide ...