LS-E2-L-BASE-PC-N Lattice, LS-E2-L-BASE-PC-N Datasheet - Page 19

• Manufacturer Part Number: LS-E2-L-BASE-PC-N
• Description: MCU, MPU & DSP Development Tools ispLEVER Base - LS ECP2 50E Std Dev Kit
• Manufacturer: Lattice

Specifications of LS-E2-L-BASE-PC-N

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Lattice Semiconductor
Table 38. SW1 Connections
SW2 is a momentary switch that, when pressed, forces the FPGA to start a configuration cycle.
SW3 is a momentary switch that the user can define for any purpose, such as a global reset. SW3 is wired to I/O
E18 (bank 1) and applies a low logic level (0) when pressed.
LEDs
Eight user-definable LEDs are provided on the top of the board under SW1. These LEDs are each wired to a sepa-
rate GPIO on bank 1 as defined in the Table 39. The current limiting resistors associated with these LEDs are wired
to 3.3V, but it is safe to drive these signals with any FPGA I/O voltage. The LED will light when its associated I/O pin
is driven low.
Table 39. LED Connections
There are also three LEDs associated with the dedicated programming pins.
Table 40. Programming LEDs
Note: During JTAG programming, the state of the DONE LED has no meaning. This is because the DONE pin,
which drives the LED, is being controlled by the pin’s BSCAN cell. See Lattice technical note number TN1108,
LatticeECP2 sysCONFIG Usage Guide, for more information on the dedicated programming pins.
Seven-Segment Display
This board contains a seven-segment display, with decimal point, at U2. The segments are wired to GPIO as
defined in Table 41. A low on the pin will turn on the associated segment.
LED
D12
D11
D10
PROGRAMN
DONE
INITN
Pin
Switch
SW1-1
SW1-2
SW1-3
SW1-4
SW1-5
SW1-6
SW1-7
SW1-8
LED
D1
D2
D3
D4
D5
D6
D7
D8
Yellow
Green
Color
Red
19
LatticeECP2 Standard Evaluation Board
C12
D12
D13
D14
C13
B12
A11
A12
E12
E13
B14
A14
E14
F14
A13
B13
Pin
Pin
On when signal is low
On when initializing
On when configuration is complete
Function
User’s Guide