74ALVCH16832DGG:11 NXP Semiconductors, 74ALVCH16832DGG:11 Datasheet - Page 2

• Manufacturer Part Number: 74ALVCH16832DGG:11
• Description: 74ALVCH16832DGG/TSSOP64/REEL13
• Manufacturer: NXP Semiconductors
• Series: 74ALVCHr

Specifications of 74ALVCH16832DGG:11

• Logic Type: 7-Bit to 28-Bit Address Driver
• Number Of Elements: 1
• Number Of Bits Per Element: 7
• Current - Output High, Low: 24mA, 24mA
• Voltage - Supply: 2.3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-TSSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 935270692118; ALVCH16832DGG-T; ALVCH16832DGG-T

outputs follow the inputs and are controlled by the two output-enable
When OE is a logic low, the outputs are in a normal logic state, (high
Philips Semiconductors
FEATURES
DESCRIPTION
This 7 channel 1-bit to 4-bit address register/driver is designed for
2.3 V to 3.6 V V
applications in which a single address bus is driving four separate
memory locations. The 74ALVCH16832 can be used as a buffer or
a register, depending on the logic level of the select (SEL) input.
When SEL is a logic high, the device is in the buffer mode. The
(OE) inputs. Each OE controls two groups of seven outputs.
When SEL is a logic low, the device is in the register mode. The
register is an edge-triggered D-type flip-flop. On the positive
transition of the clock (CLK) input, data at the A inputs is stored in
the internal registers. OE operates the same as in the buffer mode.
or low logic level). When OE is a logic high, the outputs are in the
high-impedance state.
Neither SEL of OE affect the internal operation of the flip-flops. Old
data can be retained or new data can be entered while the outputs
are in the high-impedance state.
To ensure the high-impedance state during power up or power
down, OE should be tied to V
minimum value of the resistor is determined by the current-sinking
capability of the driver.
Active buss-hold circuitry is provided to hold unused or floating data
inputs at a valid logic level.
The 74ALVCH16832 is characterized for operation from –40 to
+85 C.
PIN DESCRIPTION
ORDERING INFORMATION
1, 2, 4, 5, 28. 29, 31, 32, 33, 34,
36, 37, 41, 42, 44, 45, 47, 48, 49,
50, 54, 55, 57, 58, 60, 61, 63, 64
3, 8, 10, 14, 19, 23, 25, 30, 35,
39, 40, 46, 51, 53, 56, 62
6, 12, 22, 27, 38, 43, 52, 59
7, 9, 11, 20, 21, 24, 26
16, 17
15
18
64-pin Plastic TSSOP
2001 Dec 14
ESD protection exceeds 2000 V HBM per JESD22-A114,
200 V MM per JESD22-A115 and 1000 V CDM per JESD22-C101
Latch-up testing is done to JESDEC Standard JESD78 which
exceeds 100 mA
Bus hold on data inputs eliminates the need for external
pullup/pulldown resistors
7-bit to 28-bit address register/driver with 3-state
outputs
PACKAGES
PIN(S)
CC
operation. This device is ideal for use in
CC
through a pullup resistor; the
1Yn, 2Yn,
3Yn, 4Yn
GND
V
An
OE1, OE2
CLK
SEL
SYMBOL
CC
TEMPERATURE RANGE
–40 to +85 C
Outputs
Ground
Supply voltage
Inputs
Output enable
Clock
Select
FUNCTION
2
PIN CONFIGURATION
74ALVCH16832DGG
ORDER CODE
GND
GND
GND
GND
GND
GND
GND
GND
OE1
OE2
V
CLK
2Y1
1Y1
SEL
V
4Y7
3Y7
2Y7
1Y7
3Y1
V
V
4Y1
NC
CC
A1
A2
A3
A4
A5
CC
A6
CC
A7
CC
10
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
11
1
2
3
4
5
6
7
8
9
74ALVCH16832
135
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39 GND
38 V
37
36
34
33
DWG NUMBER
1Y2
2Y2
GND
3Y2
4Y2
V
1Y3
2Y3
GND
3Y3
4Y3
GND
V
GND
1Y4
2Y4
3Y4
4Y4
GND
1Y5
2Y5
V
3Y5
4Y5
GND
1Y6
2Y6
GND
3Y6
4Y6
SOT646-1
CC
CC
CC
CC
853-2311 27460
Product data
SV01912