AD5324BRM Analog Devices Inc, AD5324BRM Datasheet - Page 14

• Manufacturer Part Number: AD5324BRM
• Description: Digital/Analog Converter IC Interface Type:Serial
• Manufacturer: Analog Devices Inc

Specifications of AD5324BRM

• Number Of Bits: 12
• Number Of Outputs: 4
• Package/case: 10-SOIC
• A/d, D/a Features: 2.5 V To 5.5 V, 500 A Quad Voltage Output 12-Bit DAC
• Mounting Type: Surface Mount
• Rohs Status: RoHS non-compliant
• Settling Time: 6µs
• Data Interface: Serial
• Number Of Converters: 4
• Voltage Supply Source: Single Supply
• Power Dissipation (max): 5mW
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 10-MSOP, Micro10™, 10-uMAX, 10-uSOP

AD5304/AD5314/AD5324
THEORY OF OPERATION
FUNCTIONAL DESCRIPTION
The AD5304/AD5314/AD5324 are quad, resistor-string DACs
fabricated on a CMOS process with resolutions of 8, 10, and 12
bits, respectively. Each contains four output buffer amplifiers and
is written to via a 3-wire serial interface. They operate from single
supplies of 2.5 V to 5.5 V, and the output buffer amplifiers provide
rail-to-rail output swing with a slew rate of 0.7 V/μs. The four
DACs share a single reference input pin. The devices have pro-
grammable power-down modes, in which all DACs can be turned
off completely with a high impedance output.
Digital-to-Analog
The architecture of one DAC channel consists of a resistor-string
DAC followed by an output buffer amplifier. The voltage at the
REFIN pin provides the reference voltage for the DAC. Figure 30
shows a block diagram of the DAC architecture. Since the input
coding to the DAC is straight binary, the ideal output voltage is
given by
where
D = decimal equivalent of the binary code that is loaded to the
DAC register:
N = DAC resolution.
Resistor String
The resistor string section is shown in Figure 31. It is simply a
string of resistors, each of value R. The digital code loaded to the
DAC register determines at which node on the string the voltage
is tapped off to be fed into the output amplifier. The voltage is
tapped off by closing one of the switches connecting the string
to the amplifier. Because it is a string of resistors, it is guaranteed
monotonic.
REGISTER
0–255 for AD5304 (8 bits)
0–1023 for AD5314 (10 bits)
0–4095 for AD5324 (12 bits)
INPUT
V
OUT
=
V
REF
2
REGISTER
N
Figure 30. DAC Channel Architecture
×
DAC
D
RESISTOR
STRING
REFIN
OUTPUT BUFFER
AMPLIFIER
V
OUT
A
Rev. F | Page 14 of 24
DAC Reference Inputs
There is a single reference input pin for the four DACs. The ref-
erence input is not buffered. The user can have a reference voltage
as low as 0.25 V or as high as VDD because there is no restrict-
tion due to the headroom or footroom requirements of any
reference amplifier. It is recommended to use a buffered refer-
ence in the external circuit (for example, REF192). The input
impedance is typically 45 kΩ.
Output Amplifier
The output buffer amplifier is capable of generating rail-to-rail
voltages on its output, giving an output range of 0 V to V
the reference is V
GND or V
and sink capabilities of the output amplifier can be seen in the
plot in Figure 15.
The slew rate is 0.7 V/μs with a half-scale settling time to
±0.5 LSB (at eight bits) of 6 μs.
POWER-ON RESET
The AD5304/AD5314/AD5324 are provided with a power-on
reset function, so that they power up in a defined state. The power-
on state uses normal operation and an output voltage set to 0 V.
Both input and DAC registers are filled with zeros and remain
so until a valid write sequence is made to the device. This is par-
ticularly useful in applications where it is important to know the
state of the DAC outputs while the device is powering up.
SERIAL INTERFACE
The AD5304/AD5314/AD5324 are controlled over a versatile,
3-wire serial interface that operates at clock rates up to 30 MHz
and are compatible with SPI, QSPI, MICROWIRE, and DSP inter-
face standards.
DD
, in parallel with 500 pF to GND or V
R
R
R
R
R
DD
. It is capable of driving a load of 2 kΩ to
Figure 31. Resistor String
TO OUTPUT
AMPLIFIER
DD
. The source
DD
when