AD5324BRM Analog Devices Inc, AD5324BRM Datasheet - Page 7

• Manufacturer Part Number: AD5324BRM
• Description: Digital/Analog Converter IC Interface Type:Serial
• Manufacturer: Analog Devices Inc

Specifications of AD5324BRM

• Number Of Bits: 12
• Number Of Outputs: 4
• Package/case: 10-SOIC
• A/d, D/a Features: 2.5 V To 5.5 V, 500 A Quad Voltage Output 12-Bit DAC
• Mounting Type: Surface Mount
• Rohs Status: RoHS non-compliant
• Settling Time: 6µs
• Data Interface: Serial
• Number Of Converters: 4
• Voltage Supply Source: Single Supply
• Power Dissipation (max): 5mW
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 10-MSOP, Micro10™, 10-uMAX, 10-uSOP

PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
Table 5. Pin Function Descriptions
Pin No.
1
2
3
4
5
6
7
8
9
10
Exposed
Paddle
1
LFCSP package.
1
Mnemonic
V
V
V
V
REFIN
V
GND
DIN
SCLK
SYNC
GND
DD
OUT
OUT
OUT
OUT
A
B
C
D
V
V
V
REFIN
OUT
OUT
OUT
Description
Power Supply Input. These parts can be operated from 2.5 V to 5.5 V and the supply can be decoupled to GND.
Buffered Analog Output Voltage from DAC A. The output amplifier has rail-to-rail operation.
Buffered Analog Output Voltage from DAC B. The output amplifier has rail-to-rail operation.
Buffered Analog Output Voltage from DAC C. The output amplifier has rail-to-rail operation.
Reference Input Pin for All Four DACs. It has an input range from 0.25 V to V
Buffered Analog Output Voltage from DAC D. The output amplifier has rail-to-rail operation.
Ground Reference Point for All Circuitry on the Part.
Serial Data Input. This device has a 16-bit shift register. Data is clocked into the register on the falling edge of the
serial clock input. The DIN input buffer is powered down after each write cycle.
Serial Clock Input. Data is clocked into the input shift register on the falling edge of the serial clock input. Data can
be transferred at clock speeds up to 30 MHz. The SCLK input buffer is powered down after each write cycle.
Active Low Control Input. This is the frame synchronization signal for the input data. When SYNC goes low, it
enables the input shift register and data is transferred in on the falling edges of the following 16 clocks. If SYNC is
taken high before the 16
sequence is ignored by the device.
Ground Reference Point for All Circuitry on the Part. Can be connected to 0 V or left unconnected provided there is
a connection to 0 V via the GND pin.
Figure 3. MSOP Pin Configuration
V
DD
A
B
C
1
2
3
4
5
(Not to Scale)
AD5304/
AD5314/
AD5324
TOP VIEW
10
9
8
7
6
SYNC
SCLK
DIN
GND
V
OUT
th
D
falling edge of SCLK, the rising edge of SYNC acts as an interrupt and the write
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V
V
V
REFIN
OUT
OUT
OUT
Figure 4. LFCSP Pin Configuration
V
DD
A
B
C
1
2
3
4
5
(Not to Scale)
AD5304/
AD5314/
AD5324
TOP VIEW
AD5304/AD5314/AD5324
DD
.
10
9
8
7
6
SYNC
SCLK
DIN
GND
V
OUT
D