AD5324BRM Analog Devices Inc, AD5324BRM Datasheet - Page 17

• Manufacturer Part Number: AD5324BRM
• Description: Digital/Analog Converter IC Interface Type:Serial
• Manufacturer: Analog Devices Inc

Specifications of AD5324BRM

• Number Of Bits: 12
• Number Of Outputs: 4
• Package/case: 10-SOIC
• A/d, D/a Features: 2.5 V To 5.5 V, 500 A Quad Voltage Output 12-Bit DAC
• Mounting Type: Surface Mount
• Rohs Status: RoHS non-compliant
• Settling Time: 6µs
• Data Interface: Serial
• Number Of Converters: 4
• Voltage Supply Source: Single Supply
• Power Dissipation (max): 5mW
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 10-MSOP, Micro10™, 10-uMAX, 10-uSOP

AD5304/AD5314/AD5324 to 68HC11/68L11 Interface
Figure 37 shows a serial interface between the AD5304/AD5314/
AD5324 and the 68HC11/68L11 microcontroller. SCK of the
68HC11/68L11 drives the SCLK of the AD5304/AD5314/
AD5324, while the MOSI output drives the serial data line
(DIN) of the DAC. The SYNC signal is derived from a port
line (PC7). The setup conditions for correct operation of this
interface are as follows: the 68HC11/68L11 is configured so
that its CPOL bit is a 0 and its CPHA bit is a 1. When data is
being transmitted to the DAC, the SYNC line is taken low (PC7).
When the 68HC11/68L11 is configured as above, data appearing
on the MOSI output is valid on the falling edge of SCK. Serial
data from the 68HC11/68L11 is transmitted in 8-bit bytes with
only eight falling clock edges occurring in the transmit cycle.
Data is transmitted MSB first. To load data to the AD5304/
AD5314/AD5324, PC7 is left low after the first eight bits are
transferred, a second serial write operation is performed to
the DAC, and PC7 is taken high at the end of this procedure.
AD5304/AD5314/AD5324 to 80C51/80L51 Interface
Figure 38 shows a serial interface between the AD5304/AD5314/
AD5324 and the 80C51/80L51 microcontroller. The setup for
the interface is as follows: TxD of the 80C51/80L51 drives SCLK
of the AD5304/AD5314/AD5324, while RxD drives the serial
data line of the part. The SYNC signal is again derived from a
bit-programmable pin on the port. In this case, port line P3.3 is
used. When data is to be transmitted to the AD5304/AD5314/
AD5324, P3.3 is taken low. The 80C51/80L51 transmits data
Figure 37. AD5304/AD5314/AD5324 to 68HC11/68L11 Interface
*ADDITIONAL PINS OMITTED FOR CLARITY.
68HC11/68L11*
MOSI
SCK
PC7
SYNC
SCLK
DIN
AD5324*
AD5304/
AD5314/
Rev. F | Page 17 of 24
only in 8-bit bytes; thus only eight falling clock edges occur in
the transmit cycle. To load data to the DAC, P3.3 is left low after
the first eight bits are transmitted, and a second write cycle is
initiated to transmit the second byte of data. P3.3 is taken high
following the completion of this cycle. The 80C51/80L51 outputs
the serial data in a format that has the LSB first. The AD5304/
AD5314/AD5324 requires its data with the MSB as the first bit
received. The 80C51/80L51 transmit routine takes this into
account.
AD5304/AD5314/AD5324 to MICROWIRE Interface
Figure 39 shows an interface between the AD5304/AD5314/
AD5324 and any MICROWIRE-compatible device. Serial data
is shifted out on the falling edge of the serial clock, SK, and is
clocked into the AD5304/AD5314/AD5324 on the rising edge
of SK, which corresponds to the falling edge of the DAC’s SCLK.
Figure 38. AD5304/AD5314/AD5324 to 80C51/80L51 Interface
Figure 39. AD5304/AD5314/AD5324 to MICROWIRE Interface
*ADDITIONAL PINS OMITTED FOR CLARITY.
*ADDITIONAL PINS OMITTED FOR CLARITY.
80C51/80L51*
MICROWIRE*
P3.3
RxD
TxD
SO
CS
SK
AD5304/AD5314/AD5324
SYNC
SCLK
DIN
SYNC
SCLK
DIN
AD5304/
AD5314/
AD5324*
AD5304/
AD5314/
AD5324*