AD7193BCPZ Analog Devices Inc, AD7193BCPZ Datasheet - Page 2

• Manufacturer Part Number: AD7193BCPZ
• Description: 4ch VeryLow Noise 24Bit SD ADC With PGA
• Manufacturer: Analog Devices Inc

Specifications of AD7193BCPZ

• Number Of Bits: 24
• Sampling Rate (per Second): 4.8k
• Data Interface: DSP, MICROWIRE™, QSPI™, Serial, SPI™
• Number Of Converters: 1
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 105°C
• Mounting Type: Surface Mount
• Package / Case: 32-WFQFN, CSP Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD7193
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
General Description ......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
Absolute Maximum Ratings ............................................................ 9
Pin Configurations and Function Descriptions ......................... 10
Typical Performance Characteristics ........................................... 14
RMS Noise and Resolution ............................................................ 17
On-Chip Registers .......................................................................... 20
ADC Circuit Information .............................................................. 30
REVISION HISTORY
4/10—Rev. A to Rev. B
Added 32-Lead LFCSP ....................................................... Universal
Changes to Table 7 .......................................................................... 17
Changes to Communications Register, Table 16 ........................ 20
Updated Outline Dimensions ....................................................... 54
Changes to Ordering Guide .......................................................... 54
9/09—Rev. 0 to Rev. A
Changes to Internal/External Clock, Internal Clock Frequency
Parameter, Table 1 ............................................................................. 5
Changes to Figure 7 and Figure 8 ................................................. 14
Changes to Table 6 .......................................................................... 17
Changes to Table 9 .......................................................................... 18
Timing Characteristics ................................................................ 7
Thermal Resistance ...................................................................... 9
ESD Caution .................................................................................. 9
Sinc
Sinc
Fast Settling ................................................................................. 19
Communications Register ......................................................... 21
Status Register ............................................................................. 22
Mode Register ............................................................................. 23
Configuration Register .............................................................. 26
Data Register ............................................................................... 28
ID Register ................................................................................... 28
GPOCON Register ..................................................................... 28
Offset Register ............................................................................. 29
Full-Scale Register ...................................................................... 29
Overview ...................................................................................... 30
Analog Input Channel ............................................................... 31
Programmable Gain Array (PGA) ........................................... 31
4
3
Chop Disabled ................................................................... 17
Chop Disabled ................................................................... 18
Rev. B | Page 2 of 56
Digital Filter .................................................................................... 40
Grounding and Layout .................................................................. 52
Applications Information .............................................................. 53
Outline Dimensions ....................................................................... 54
Changes to Table 12, Table 13, and Table 14 ............................... 19
Changes to Table 19 ....................................................................... 24
Changes to Table 22 and Table 23 ................................................ 27
Changes to Offset Register and Full-Scale Register Sections ... 29
Changes to Reference Section ....................................................... 31
Changes to Data Output Coding Section .................................... 32
Changes to Sinc
Changes to Sinc
Changes to 50 Hz/60 Hz Rejection, Sinc
Changes to Summary of Filter Options Section and Table 35 .. 52
7/09—Revision 0: Initial Version
Reference ..................................................................................... 31
Reference Detect ......................................................................... 32
Bipolar/Unipolar Configuration .............................................. 32
Data Output Coding .................................................................. 32
Burnout Currents ....................................................................... 32
Channel Sequencer .................................................................... 32
Digital Interface .......................................................................... 33
Reset ............................................................................................. 37
System Synchronization ............................................................ 37
Enable Parity ............................................................................... 37
Clock ............................................................................................ 37
Bridge Power-Down Switch ...................................................... 37
Temperature Sensor ................................................................... 38
Logic Outputs ............................................................................. 38
Calibration ................................................................................... 38
Sinc
Sinc3 Filter (Chop Disabled) .................................................... 42
Chop Enabled (Sinc
Chop Enabled (Sinc
Fast Settling Mode (Sinc
Fast Settling Mode (Sinc
Fast Settling Mode (Chop Enabled) ......................................... 50
Summary of Filter Options ....................................................... 51
Flowmeter .................................................................................... 53
Ordering Guide .......................................................................... 54
4
Filter (Chop Disabled) ..................................................... 40
4
3
50 Hz/60 Hz Rejection Section ...................... 41
50 Hz/60 Hz Rejection Section ...................... 43
4
3
Filter) ...................................................... 44
Filter) ...................................................... 46
4
3
Filter) ............................................... 47
Filter) ............................................... 49
4
Filter Section ........... 47