AD7193BCPZ Analog Devices Inc, AD7193BCPZ Datasheet - Page 36

• Manufacturer Part Number: AD7193BCPZ
• Description: 4ch VeryLow Noise 24Bit SD ADC With PGA
• Manufacturer: Analog Devices Inc

Specifications of AD7193BCPZ

• Number Of Bits: 24
• Sampling Rate (per Second): 4.8k
• Data Interface: DSP, MICROWIRE™, QSPI™, Serial, SPI™
• Number Of Converters: 1
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 105°C
• Mounting Type: Surface Mount
• Package / Case: 32-WFQFN, CSP Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD7193
Continuous Read
Rather than write to the communications register each time a
conversion is complete to access the data, the AD7193 can be
configured so that the conversions are placed on the DOUT/
RDY line automatically. By writing 01011100 to the communi-
cations register, the user need only apply the appropriate number
of SCLK cycles to the ADC, and the conversion word is auto-
matically placed on the DOUT/ RDY line when a conversion is
complete. The ADC should be configured for continuous
conversion mode.
When DOUT/ RDY goes low to indicate the end of a conversion,
sufficient SCLK cycles must be applied to the ADC; the data
conversion is then placed on the DOUT/ RDY line. When the
conversion is read, DOUT/ RDY returns high until the next
conversion is available. In this mode, the data can be read only
once. The user must also ensure that the data-word is read
before the next conversion is complete. If the user has not read
the conversion before the completion of the next conversion, or
if insufficient serial clocks are applied to the AD7193 to read
the word, the serial output register is reset when the next
conversion is complete, and the new conversion is placed in the
output serial register.
DOUT/RDY
SCLK
DIN
CS
0x5C
Figure 27. Continuous Read
Rev. B | Page 36 of 56
DATA
To exit the continuous read mode, Instruction 01011000 must
be written to the communications register while the RDY pin
is low. While in the continuous read mode, the ADC monitors
activity on the DIN line so that it can receive the instruction to
exit the continuous read mode. Additionally, a reset occurs if
40 consecutive 1s are seen on DIN. Therefore, DIN should be
held low in continuous read mode until an instruction is to be
written to the device.
When several channels are enabled, the ADC continuously
steps through the enabled channels and performs one conversion
on each channel each time that it is selected. DOUT/ RDY pulses
low when a conversion is available. When the user applies sufficient
SCLK pulses, the data is automatically placed on the DOUT/ RDY
pin. If the DAT_STA bit in the mode register is set to 1, the
contents of the status register are output along with the conversion.
The status register indicates the channel to which the conversion
corresponds.
DATA
DATA