AD7193BCPZ Analog Devices Inc, AD7193BCPZ Datasheet - Page 40

• Manufacturer Part Number: AD7193BCPZ
• Description: 4ch VeryLow Noise 24Bit SD ADC With PGA
• Manufacturer: Analog Devices Inc

Specifications of AD7193BCPZ

• Number Of Bits: 24
• Sampling Rate (per Second): 4.8k
• Data Interface: DSP, MICROWIRE™, QSPI™, Serial, SPI™
• Number Of Converters: 1
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 105°C
• Mounting Type: Surface Mount
• Package / Case: 32-WFQFN, CSP Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD7193
DIGITAL FILTER
The AD7193 offers a lot of flexibility in the digital filter. The
device has five filter options. The device can be operated with
a sinc
latency can be enabled. Finally, an averaging block can be
included after the sinc filter, which gives a fast settling mode.
The option selected affects the output data rate, settling time,
and 50 Hz/60 Hz rejection. The following sections describe
each filter type, indicating the available output data rates for
each filter option. The filter response, along with the settling
time and 50 Hz/60 Hz rejection, is also discussed.
SINC
When the AD7193 is powered up, the sinc
default and chop is disabled. This filter gives excellent noise
performance over the complete range of output data rates. It
also gives the best 50 Hz/60 Hz rejection, but it has a long
settling time.
Sinc
The output data rate (the rate at which conversions are available
on a single channel when the ADC is continuously converting)
is equal to
where:
f
f
FS[9:0] is the decimal equivalent of Bit FS9 to Bit FS0 in the
mode register.
The output data rate can be programmed from 4.7 Hz to
4800 Hz; that is, FS[9:0] can have a value from 1 to 1023.
The settling time for the sinc
When a channel change occurs, the modulator and filter are
reset. The settling time is allowed to generate the first conver-
sion after the channel change. Subsequent conversions on this
channel occur at 1/f
ADC
CLK
CONVERSIONS
is the master clock (4.92 MHz nominal).
is the output data rate.
4
f
t
ADC
3
SETTLE
CHANNEL
4
Output Data Rate/Settling Time
or sinc
FILTER (CHOP DISABLED)
= f
CHOP
= 4/f
CLK
4
/(1024 × FS[9:0])
filter, chop can be enabled or disabled, and zero
CH A CH A CH A
ADC
Figure 28. Sinc
CHANNEL A
MODULATOR
Figure 29. Sinc
ADC
.
4
4
Filter (Chop Disabled)
filter is equal to
4
ADC
SINC
Channel Change
3
/SINC
1/
CHANNEL B
f
ADC
4
4
filter is selected by
POST FILTER
CH B CH B CH B
Rev. B | Page 40 of 56
When conversions are performed on a single channel and a step
change occurs, the ADC does not detect the change in analog
input. Therefore, it continues to output conversions at the pro-
grammed output data rate. However, it is at least four conversions
later before the output data accurately reflect the analog input.
If the step change occurs while the ADC is processing a conver-
sion, then the ADC takes five conversions after the step change
to generate a fully settled result.
The 3 dB frequency for the sinc
Table 28 gives some examples of the relationship between the
values in Bits FS[9:0] and the corresponding output data rate
and settling time.
Table 28. Examples of Output Data Rates and the
Corresponding Settling Time
FS[9:0]
480
96
80
Sinc
Zero latency is enabled by setting the single bit (Bit 11) in the
mode register to 1. With zero latency, the complete settling time
is allowed for each conversion. Therefore, the conversion time
when converting on a single channel or when converting on
several channels is constant. The user does not need to consider
the effects of channel changes on the output data rate. When the
channel sequencer is enabled, the AD7193 automatically
operates in zero latency mode.
The output data rate equals
where:
f
f
FS[9:0] is the decimal equivalent of Bit FS9 to Bit FS0 in the
mode register.
ADC
CLK
ANALOG
OUTPUT
is the master clock (4.92 MHz nominal).
INPUT
is the output data rate.
f
4
f
ADC
3dB
ADC
Zero Latency
1/
= 0.23 × f
f
= 1/t
ADC
Figure 30. Asynchronous Step Change in Analog Input
Output Data Rate (Hz)
10
50
60
SETTLE
ADC
= f
CLK
/(4 × 1024 × FS[9:0])
4
filter is equal to
Settling Time (ms)
400
80
66.6
SETTLED
FULLY