AD9522-5/PCBZ Analog Devices Inc, AD9522-5/PCBZ Datasheet - Page 38

• Manufacturer Part Number: AD9522-5/PCBZ
• Description: 12/24 Channel Clock Gen 2,0GH
• Manufacturer: Analog Devices Inc

Specifications of AD9522-5/PCBZ

• Main Purpose: Timing, Clock Generator
• Embedded: No
• Utilized Ic / Part: AD9522-5
• Primary Attributes: 12 LVDS/24 CMOS Outputs
• Secondary Attributes: I²C & SPI Interfaces
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD9522-5
CLOCK DISTRIBUTION
A clock channel consists of three LVDS clock outputs or six
CMOS clock outputs that share a common divider. A clock
output consists of the drivers that connect to the output pins.
The clock outputs have either LVDS or CMOS at the pins.
The AD9522 has four clock channels. Each channel has its own
programmable divider that divides the clock frequency applied
to its input. The channel dividers can divide by any integer
from 1 to 32.
The AD9522 features a VCO divider that divides the VCO output
by 1, 2, 3, 4, 5, or 6 before going to the individual channel dividers.
The VCO divider has two purposes. The first is to limit the
maximum input frequency of the channel dividers to 1.6 GHz.
The other is to allow the AD9522 to generate even lower
frequencies than would be possible with only a simple post divider.
The channel dividers allow for a selection of various duty cycles,
depending on the currently set division. That is, for any specific
division, D, the output of the divider can be set to high for N + 1
input clock cycles and low for M + 1 input clock cycles (where
D = N + M + 2). For example, a divide-by-5 can be high for one
divider input cycle and low for four cycles, or a divide-by-5 can
be high for three divider input cycles and low for two cycles.
Other combinations are also possible.
The channel dividers include a duty-cycle correction function
that can be disabled. In contrast to the selectable duty cycle
just described, this function can correct a non-50% duty cycle
caused by an odd division. However, this requires that the
division be set by M = N + 1.
In addition, the channel dividers allow a coarse phase offset or
delay to be set. Depending on the division selected, the output
can be delayed by up to 15 input clock cycles. For example, if
the frequency at the input of the channel divider is 1 GHz, the
channel divider output can be delayed by up to 15 ns. The
divider outputs can also be set to start high or to start low.
CLK
CLK
MODE 1 (CLOCK DISTRIBUTION MODE)
Figure 37. Simplified Diagram of the Two Clock Distribution Operation Modes
DISTRIBUTION
CLOCK
2, 3, 4, 5, OR 6
DIVIDE BY 1,
1
0
PLL
BUTION
CLOCK
DISTRI-
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CLK
CLK
MODE 2 (HF CLOCK DISTRIBUTION MODE)
Operation Modes
The AD9522-5 has two clock distribution operating modes that
are shown in Figure 37.
It is not necessary to use the VCO divider if the CLK frequency
is less than the maximum channel divider input frequency
(1600 MHz); otherwise, the VCO divider must be used to
reduce the frequency going to the channel dividers.
Table 26 shows how the operation modes are selected. 0x1E1[0]
selects the channel divider source.
Table 26. Operation Modes
Mode
2
1
Clock Frequency Division
The total frequency division is a combination of the VCO
divider (when used) and the channel divider. When the VCO
divider is used, the total division from the CLK input to the
output is the product of the VCO divider (1, 2, 3, 4, 5, or 6)
and the division of the channel divider. Table 27 indicates how
the frequency division for a channel is set.
Table 27. Frequency Division
VCO Divider
Setting
1 to 6
2 to 6
1
VCO divider
bypassed
VCO divider
bypassed
1
The bypass VCO divider (0x1E1[0] = 1) is not the same as VCO divider = 1.
1
0x1E1[0]
0
1
Channel Divider
Setting
2 to 32
Bypass
Bypass
Bypass
2 to 32
DISTRIBUTION
CLOCK
2, 3, 4, 5, OR 6
1
DIVIDE BY 1,
0
PLL
BUTION
CLOCK
DISTRI-
Resulting Frequency
Division
(1 to 6) × (2 to 32)
(2 to 6) × (1)
Output static (illegal state)
1
2 to 32
VCO Divider
Used
Not used